Method for controlling non-volatile semiconductor memory system by using look up table

• US 6,845,438 B1
• Filed: 08/07/1998
• Issued: 01/18/2005
• Est. Priority Date: 08/08/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawamoto, Kazuya, Tanaka, Yoshiyuki, Sato, Takeaki, Yatabe, Makoto
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US09/130,818
• Time in Patent Office: 2,356 Days
• Field of Search: 711/4, 711/5, 711/103, 711/206, 711/207
• US Class Current: 711/206
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.

Claims

1. A method for controlling a non-volatile semiconductor memory system, the method comprising:

defining a plurality of physical blocks in a cell array of non-volatile semiconductor memory cells, each of the physical blocks including a plurality of non-volatile memory cells adapted for storing data;

storing address mapping information between the physical blocks and corresponding logical blocks in the physical blocks;

defining within the cell array at least first and second zones, each zone including at least one of the physical blocks;

preparing, in response to a power supply being turned on, a prepared address translation table comprising address translation information between logical blocks and physical blocks within the memory array, the prepared address translation table including address translation information for logical block addresses within at least the first zone and not including address translation information for logical block addresses within at least the second zone; and

determining that a requested logical block is not within the prepared address translation table and subsequently preparing a second address translation table comprising address translation information for logical block addresses within the second zone.

2. A method for controlling a non-volatile semiconductor memory system, as set forth in claim 1, the method further comprising selectively replacing a defective physical block including defective cells with a redundant physical block so that, for each area, a quantity of defective physical blocks is less than or equal to a predetermined number.

3. A method for controlling a non-volatile semiconductor memory system, the method comprising:

dividing a cell array of non-volatile semiconductor memory cells into a plurality of physical blocks;

storing in each of the physical blocks information corresponding to each relationship between the physical blocks and corresponding ones of logical blocks managed by the system;

storing in a random access memory in the system a first table for managing corresponding relationships between a first set of the logical blocks and the physical blocks of a first physical block zone including one or more of the physical blocks; and

determining in response to an access from a host that a requested logical block is not within the first table and subsequently storing in the random access memory a second table comprising relationships between a second set of the logical blocks and the physical blocks of a second physical block zone including one or more of the physical blocks.

4. A method for controlling a non-volatile semiconductor memory system, as set forth in claim 3, the method further comprising selectively replacing a defective physical block including defective cells with a redundant physical block so that, for each area, a quantity of defective physical blocks is less than or equal to a predetermined number.