Device and system for adjusting delay in a data path based on comparison of data from a latch and data from a register

• US 6,845,460 B2
• Filed: 01/30/2004
• Issued: 01/18/2005
• Est. Priority Date: 11/09/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Ryan, Kevin J., Lee, Terry R.
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): Trujillo, James K.
• Application Number:
  US10/767,273
• Publication Number:
  US 20040187046A1
• Time in Patent Office: 354 Days
• Field of Search: 713/400, 713/401, 713/500, 713/600, 365/233, 365/230.01, 327/284, 711/167
• US Class Current: 713/401
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Claims

1. A device, comprising:

a functional circuit, said functional circuit comprising;

a logic circuit; and

a variable delay; and

a latch;

wherein

said variable delay is coupled to receive input from a data path and coupled to provide output to the latch; and

said latch is coupled to receive input from the variable delay and provide input to said logic circuit; and

a control circuit, said control circuit comprising;

a register;

a repeater;

a comparator; and

a command detector;

wherein

said register is coupled to receive input from a first external source and coupled to provide output to said repeater and said comparator;

said repeater is coupled to receive input from said register and said command detector and to provide output to a second external source;

said command detector is coupled to receive input from said second external source and to provide output to said repeater and said comparator; and

said comparator is coupled to receive input from said latch of said functional circuit and said register and provide output to control said variable delay.

2. The device of claim 1, wherein said device is a memory device and said logic circuit comprise a memory array.

3. The device of claim 2, wherein said memory array comprises a plurality of dynamic random access memory (DRAM) cells.

4. The device of claim 1, wherein said first external source is a register coupled to said device and said second external source is a bus coupled to said device.

5. The device of claim 4, wherein said device is a memory controller and said logic circuit comprise a control logic for controlling a memory device.

6. The device of claim 5, wherein said control logic is capable of operating a dynamic random access memory (DRAM) device.

7. A system, comprising:

a bus;

a pattern register;

a first device, said first device coupled to said bus and said first device comprising;

a first functional circuit, said first functional circuit comprising;

a first logic circuit; and

a first variable delay; and

a first latch;

wherein

said first variable delay is coupled to receive input from a data path and coupled to provide output to the first latch; and

said first latch is coupled to receive input from the first variable delay and provide input to said first logic circuit; and

a first control circuit, said first control circuit comprising;

a first register;

a first repeater;

a first comparator; and

a first command detector;

wherein

said first register is coupled to receive input from said pattern register and coupled to provide output to said repeater and said first comparator;

said first repeater is coupled to receive input from said first register and said command detector and to provide output to said bus;

said first command detector is coupled to receive input from said bus and to provide output to said repeater and said first comparator; and

said first comparator is coupled to receive input from said latch of said first functional circuit and said first register and provide output to control said first variable delay; and

a second device, said second device coupled to the bus and said second device comprising;

a second functional circuit, said second functional circuit comprising;

a second logic circuit; and

a second variable delay; and

a second latch;

wherein

said second variable delay is coupled to receive input from the data path and coupled to provide output to the second latch; and

said second latch is coupled to receive input from the second variable delay and provide input to said second logic circuit; and

a second control circuit, said second control circuit comprising;

a second register;

a second repeater;

a second comparator; and

a second command detector;

wherein

said second register is coupled to receive input from said bus and coupled to provide output to said repeater and said second comparator;

said second repeater is coupled to receive input from said second register and said command detector and to provide output to said bus;

said second command detector is coupled to receive input from said bus and to provide output to said repeater and said second comparator; and

said second comparator is coupled to receive input from said latch of said second functional circuit and said second register and provide output to control said second variable delay.

8. The system of claim 7, wherein said first device is a memory controller.

9. The system of claim 7, wherein said second device is a memory device.