Method for testing for the presence of faults in digital circuits

• US 6,845,479 B2
• Filed: 03/14/2001
• Issued: 01/18/2005
• Est. Priority Date: 03/14/2001
• Status: Active Grant

• Current Assignee: Tality UK Limited
• Original Assignee: Tality UK Limited
• Inventors: Illman, Richard
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US09/808,325
• Publication Number:
  US 20020133776A1
• Time in Patent Office: 1,406 Days
• Field of Search: 714/741, 714/724, 714/728, 714/735, 714/736, 714/737, 714/738, 714/739, 714/726, 714/715, 714/720, 703 13- 22, 324/73, 326/16, 326 21- 34, 708250-256, 708270-290, 327100-334, 345/26, 345/345, 345/551
• US Class Current: 714/739
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list F_N and then forming a vector set T_N−1 and then simulating the vector set T_N−1 against the fault list F_N. Any vector from the set T_N−1 which does not detect any fault is discarded and the remaining vectors are saved as vector set T_N. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set T_F.

Claims

1. A method of maximising the fault coverage on an integrated digital circuit by re-ordering a number of test vectors for testing the digital circuit, said method comprising:

a) providing an initial set of test vectors T₀;

b) providing an original set of faults F₀;

c) selecting faults at pseudo-random from the original fault list to form a sample fault list F_N;

d) forming a vector set T<sub>N−

1</sub> and simulating the vector set T<sub>N−

1</sub> against fault list F_N;

e) discarding any vector from the vector set T<sub>N−

1</sub> which does not detect any faults;

f) saving the remaining vectors as vector set T_N;

g) repeating the above steps c) to f) M times with N having a value of 1 to M so that at the end of M steps, test vector sets T₁ to T_M are saved;

h) removing duplicate vector patterns in each vector set T_N; and

i) saving the duplicate free vector set V_N with N having a value 1 to M, initialising the final vector set and appending vector sets V_M through V₀ to produce a final vector set T_F.

2. A method as claimed in claim 1 wherein in step g) M is 10 and steps c) to f) are therefore repeated ten times.

3. A method as claimed in claim 2 wherein the list of faults selected from the original list of faults have a probability of X⁻

N to produce subset fault list F_N.

4. A method as claimed in claim 1 wherein the list of faults selected from the original list of faults have a probability of X⁻

N to produce subset fault list F_N.

5. A method as claimed in claim 4 wherein X=2.

6. A method as claimed in claim 1 wherein the step of removing duplicate vector patterns is achieved by:

j) copying the original fault list F_O to provide a secondary fault list G_N;

k) fault simulating vector set T_N against G_N and deleting any vectors which find no faults;

l) saving the resulting vectors as vector set V_N and saving the list of undetected faults as list G<sub>N−

1</sub>;

m) repeating steps k) and 1) M times with N having values M to 1.

7. A method as claimed in claim 1 wherein the step of removing duplicate vector patterns is achieved by conducting a text search through the list of files of vector patterns looking for identical patterns, identifying the identical patterns and deleting the identical patterns identified.