Method for testing for the presence of faults in digital circuits
First Claim
1. A method of maximising the fault coverage on an integrated digital circuit by re-ordering a number of test vectors for testing the digital circuit, said method comprising:
- a) providing an initial set of test vectors T0;
b) providing an original set of faults F0;
c) selecting faults at pseudo-random from the original fault list to form a sample fault list FN;
d) forming a vector set TN−
1 and simulating the vector set TN−
1 against fault list FN;
e) discarding any vector from the vector set TN−
1 which does not detect any faults;
f) saving the remaining vectors as vector set TN;
g) repeating the above steps c) to f) M times with N having a value of 1 to M so that at the end of M steps, test vector sets T1 to TM are saved;
h) removing duplicate vector patterns in each vector set TN; and
i) saving the duplicate free vector set VN with N having a value 1 to M, initialising the final vector set and appending vector sets VM through V0 to produce a final vector set TF.
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Abstract
A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FN and then forming a vector set TN−1 and then simulating the vector set TN−1 against the fault list FN. Any vector from the set TN−1 which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set TF.
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Citations
7 Claims
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1. A method of maximising the fault coverage on an integrated digital circuit by re-ordering a number of test vectors for testing the digital circuit, said method comprising:
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a) providing an initial set of test vectors T0;
b) providing an original set of faults F0;
c) selecting faults at pseudo-random from the original fault list to form a sample fault list FN;
d) forming a vector set TN−
1 and simulating the vector set TN−
1 against fault list FN;
e) discarding any vector from the vector set TN−
1 which does not detect any faults;
f) saving the remaining vectors as vector set TN;
g) repeating the above steps c) to f) M times with N having a value of 1 to M so that at the end of M steps, test vector sets T1 to TM are saved;
h) removing duplicate vector patterns in each vector set TN; and
i) saving the duplicate free vector set VN with N having a value 1 to M, initialising the final vector set and appending vector sets VM through V0 to produce a final vector set TF. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification