Wafer-level package for micro-electro-mechanical systems

• US 6,846,725 B2
• Filed: 01/27/2003
• Issued: 01/25/2005
• Est. Priority Date: 10/17/2002
• Status: Expired due to Fees

• Current Assignee: Institute of Microelectronics
• Original Assignee: Institute of Microelectronics
• Inventors: Chen, Yu, Premachandran, Chirayarikathuveedu Sankarapillai, Nagarajan, Ranganathan, Kripesh, Vaidyanathan
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/351,534
• Publication Number:
  US 20040077154A1
• Time in Patent Office: 729 Days
• Field of Search: 438/455, 438/456, 438/106
• US Class Current: 438/456
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

Claims

1. A method for forming wafers having through-wafer vias for forming interconnects for wafer-level packaging of devices, the method comprising the steps of:

depositing metal on one of two wafers;

bonding the two wafers using the metal deposited on the one of the two wafers;

forming a through-wafer via in one of the two wafers;

filling the through-wafer via with a conductive material; and

forming a cavity in the one of the two wafers having the through-wafer via, wherein the cavity is superposable over a device, wherein the conductive material first fills by one of electroplating and electroless plating the through-wafer via at the side of the one of the two wafers having the through-wafer via to which the other of the one of the two wafers is bondable.

2. The method as in claim 1, wherein the step of forming the through-wafer via comprises the step of etching the through-wafer via in the one of the two wafers.

3. The method as in claim 1, wherein the step of forming the cavity comprises the step of etching the cavity in the one of the two wafers having the through-wafer via.

4. The method as in claim 1, wherein the step of bonding the first wafer and the second wafer comprises the step of thermocompressing the two wafers.

5. The method as in claim 1, wherein the step of forming a cavity comprises the step of forming the cavity for superposing a MEMS device requiring unimpeded movement.

6. The method as in claim 5, wherein the step of forming a cavity further comprises the step of providing substantial clearance for enabling unimpeded movement of a moving structure of the MEMS device.

7. The method as in claim 1, wherein the step of bonding the two wafers is performed subsequent to the step of forming the through-wafer via in the one of the two wafers.

8. The method as in claim 7, wherein the step of forming the through-wafer via is performed on the one of the two wafers and the other of the two wafers is a sacrificial wafer.

9. The method as in claim 8, further comprising the step of removing the sacrificial wafer, which is performed subsequent to the step of filling the through-wafer via.

10. The method as in claim 7, wherein the step of forming the through-wafer via is performed on the one of the two wafers and the device is formable in the other of the two wafers.

11. The method as in claim 10, wherein the step of forming the cavity comprises the step of forming the cavity for superposing over the device formed in the other of the two wafers.

12. The method as in claim 1, wherein the step of bonding the two wafers is performed prior to the step of forming the through-wafer via in the one of the two wafers.

13. The method as in claim 12, wherein the step of forming the through-wafer via is performed on the one of the two wafers and the other of the two wafers is a sacrificial wafer.

14. The method as in claim 13, further comprising the step of removing the sacrificial wafer, which is performed subsequent to the step of filling the through-wafer via.

15. The method as in claim 12, wherein the step of forming the through-wafer via is performed on the one of the wafers and the device is formed in the other of the two wafers.

16. The method as in claim 15, wherein the step of forming the cavity comprises the step of forming the cavity for superposing over the device formed in the other of the two wafers.

17. A method for forming wafers having through-wafer vias for forming interconnects for wafer-level packaging of devices, the method comprising the steps of:

depositing metal on one of two wafers;

bonding the two wafers using the metal deposited on the one of the two wafers;

forming a through-wafer via in one of the two wafers; and

filling the through-wafer via with a conductive material wherein the conductive material first fills by one of electroplating and electroless plating the through-wafer via at the side of the one of the two wafers having the through-wafer via to which the other of the one of the two wafers is bondable.

18. The method as in claim 17, wherein the step of forming the through-wafer via comprises the step of forming the through-wafer via in a carrier wafer containing a device for providing a 3-dimensional package by stacking at least two carrier wafers.