Method and process to make multiple-threshold metal gates CMOS technology

• US 6,846,734 B2
• Filed: 11/20/2002
• Issued: 01/25/2005
• Est. Priority Date: 11/20/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Boyd, Diane C., Kanarsky, Thomas S., Cabral, Cyril Jr., Amos, Ricky, Kedzierski, Jakub Tadeusz, Barmak, Katayun, Leong, Meikei
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US10/300,165
• Publication Number:
  US 20040094804A1
• Time in Patent Office: 797 Days
• Field of Search: 257/369, 257/413, 257/407, 257/347, 257/402, 257/350, 257/412, 438/199, 438/652, 438/217, 438/647, 438/289, 438/655, 438/585, 438/642, 438/587, 438/649, 438/588, 438/651, 438/592, 438/149, 438/664, 438/479, 438/517, 438/153, 438/154
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

Claims

1. A method of forming a metal-gated CMOS device comprising the steps of:

providing a structure which comprises a plurality of patterned gate regions located atop a Si-containing layer, each of said patterned gate regions including at least a patterned polysilicon region;

forming a first metal on each of a first predetermined number of said patterned gate regions, said first metal is in contact with said patterned polysilicon region of each of said first predetermined number of said patterned gate regions;

forming a second metal on said first metal as well as each of a second predetermined number of said patterned gate regions, wherein said second metal in each of said second predetermined number of said patterned gate region is in contact with said patterned polysilicon region of each of said second predetermined number of said patterned gate regions; and

annealing so as to cause reaction between the first and second metals and underlying patterned polysilicon regions and subsequent formation of silicide regions, where each of said first predetermined number of patterned gate regions comprises an alloy silicide of the first and second metals and each of said second predetermined number of patterned gate regions comprises a silicide of said second metal.

2. The method of claim 1 wherein said first metal and said second metal have different Fermi levels.

3. The method of claim 2 wherein said first metal comprises Co, Ni, Ti, W, Mo or Ta.

4. The method of claim 2 wherein said second metal comprises Co, Ni, Ti, W, Mo, or Ta.

5. The method of claim 1 wherein said first metal is Co and said second metal is Ni.

6. The method of claim 1 wherein said annealing is performed at a temperature of from about 450°

C. to about 900°

C. for a time period of from about 15 to about 90 seconds.

7. The method of claim 1 wherein said annealing is performed in He, Ar, N₂ or a forming gas.

8. A method of forming a metal-gated CMOS device comprising the steps of:

providing a structure which comprises a plurality of patterned gate regions located atop a Si-containing layer, each of said patterned gate regions including at least a patterned polysilicon region;

forming a first metal on each of a first predetermined number of said patterned gate regions, said first metal is in contact with each at said patterned polysilicon region of each of said first predetermined number of said patterned gate regions;

first annealing said first metal to provide a first metal silicide in each of said first predetermined number of said patterned gate regions;

forming a second metal atop the first metal silicide as well as on each of a second predetermined number of patterned gate regions, said second metal in each of said second predetermined number of patterned gate regions is in contact with said patterned polysilicon region of each of said second predetermined number of said patterned gate regions; and

second annealing said second metal to form a second metal silicide region, wherein each of said first predetermined number of patterned gate regions comprises at least an alloy silicide of said first and second metals, and each of said second predetermined number of patterned gate regions comprises said second metal silicide region.

9. The method of claim 8 wherein said first metal and said second metal have different Fermi levels.

10. The method of claim 9 wherein said first metal comprises Co, Ni, Ti, W, Mo or Ta.

11. The method of claim 9 wherein said second metal comprises Co, Ni, Ti, W, Mo, or Ta.

12. The method of claim 8 wherein said first metal is Co and said second metal is Ni.

13. The method of claim 8 wherein said first annealing is performed at a temperature of from about 450°

C. to about 600°

C. for a time period of from about 1 to about 120 seconds.

14. The method of claim 8 wherein said first annealing is performed in He, Ar, N₂ or a forming gas.

15. The method of claim 8 wherein said second annealing is performed at a temperature of from about 600°

C. to about 850°

C. for a time period of from about 1 to about 60 seconds.

16. The method of claim 8 wherein said second annealing is performed in He, Ar, N₂ or a forming gas.

17. A method of forming a metal-gated CMOS device comprising the steps of:

providing a structure which comprises a plurality of patterned gate regions located atop a Si-containing layer, each of said patterned gate regions including at least a patterned polysilicon region;

forming a dielectric stack on exposed surfaces of said Si-containing layer, said dielectric stack having an upper surface that is coplanar with said patterned polysilicon region of each of said patterned gate regions;

forming a metal alloy layer atop said upper surface of said dielectric stack and an exposed surface of said patterned polysilicon region of each of said patterned gate regions, said metal alloy layer comprising a metal and at least one alloying additive;

forming a capping layer atop said metal alloy layer;

first annealing to form a partial silicide region in an upper portion of each of said patterned gate regions;

selectively removing said capping layer; and

second annealing to convert a remaining portion of each of said patterned gate regions and said partial silicide region of each of said patterned gate regions into a metal alloy silicide region.

18. The method of claim 17 wherein said metal alloy layer comprises a metal and an alloying additive.

19. The method of claim 18 wherein said metal of said metal alloy layer comprises Co, Ni, Ti, W, Mo or Ta.

20. The method of claim 18 wherein said alloying additive comprises C, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Hf, Ta, W, Re, Ir, Pt, or mixtures thereof, with the proviso that the alloy additive is not the same as the metal.

21. The method of claim 20 wherein said alloying additive comprises Al, Ti, V, Ge, Zr, Nb, Ru, Rh, Ag, In, Sn, Ta, Re, Ir, or Pt.

22. The method of claim 18 wherein said metal alloy layer contains from about 0.1 to about 50 atomic % of said alloying additive.

23. The method of claim 17 wherein said first annealing is performed at a temperature of from about 450°

C. to about 600°

C. for a time period of from about 1 to about 120 seconds.

24. The method of claim 17 wherein said first annealing is performed in He, Ar, N₂ or a forming gas.

25. The method of claim 17 wherein said second annealing is performed at a temperature of from about 600°

C. to about 850°

C. for a time period of from about 1 to about 60 seconds.

26. The method of claim 17 wherein said second annealing is performed in He, Ar, N₂ or a forming gas.

27. The method of claim 17 wherein said metal alloy comprises Co with Sn.