Enhanced retention time for embedded dynamic random access memory (DRAM)

• US 6,847,076 B1
• Filed: 10/01/2003
• Issued: 01/25/2005
• Est. Priority Date: 10/01/2003
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsou, George T. C., Chiang, Kevin W. C., Kao, Ted T. C.
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US10/677,156
• Time in Patent Office: 482 Days
• Field of Search: 257296-313, 438/238, 438/239
• US Class Current: 257/296
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto

Abstract

Increasing the retention time of an embedded dynamic random access memory (DRAM) is disclosed. An embedded DRAM includes a metal oxide semiconductor (MOS) capacitor. The capacitor has a storage node formed between a P+ doped region and a polysilicon plate within an N well. An N− doped region is situated substantially completely under the polysilicon plate and substantially under the P+ doped region. The presence of the N− doped region decreases the threshold voltage of the capacitor and reduces effectively the junction leakage current to the N well, achieving a larger retention time.

Claims

1. An embedded dynamic random access memory (DRAM) comprising:

a metal oxide semiconductor (MOS) capacitor having a storage node formed between a P+ doped region and a polysilicon plate; and

,

an N−

doped region by adding an extra P-type implantation which is substantially completely under the polysilicon plate and substantially under the P+ doped region, to decrease a threshold voltage of the capacitor and degrading the gradient of the PN junction doping profile between storage node and N-Well.

2. The embedded DRAM of claim 1, wherein the MOS capacitor has a junction leakage current that is decreased due to the degraded PN junction doping profile resulted from the N−

doped region.

3. The embedded DRAM of claim 1, wherein the N-doped region is formed by adding extra P-type dosages in N-Well region beneath the MOS capacitor or just using native N-Well implant without any Vt adjustment, pocket or channel implant.

4. The embedded DRAM of claim 1, wherein the MOS capacitor has a threshold voltage that is decreased due to the N−

doped region.

5. The embedded DRAM of claim 1, wherein the N−

doped region is fabricated at least in part by using an existing semiconductor mask.

6. The embedded DRAM of claim 1, further comprising an N well in which the P+ doped region and the N−

doped region are situated, the polysilicon plate situated over the N well.

7. The embedded DRAM of claim 6, wherein the N well is biased negative at a voltage Vdd.

8. The embedded DRAM of claim 1, further comprising a second P+ doped region.

9. The embedded DRAM of claim 8, further comprising a transfer gate over and between the P+ doped region and the second P+ doped region.

10. The embedded DRAM of claim 9, wherein the transfer gate has applied thereto a Vbb turn-on voltage to turn on the embedded DRAM and a Vpp turn-off voltage to turn off the embedded DRAM.

11. An embedded dynamic random access memory (DRAM) comprising:

an N well biased at a negative voltage;

a metal oxide semiconductor (MOS) capacitor having a storage node formed between a P+ doped region in the N well and a polysilicon plate over the N well; and

,

a N−

doped region in the N well substantially completely under the polysilicon plate and substantially under the P+ doped region, to increase a retention time of the storage node of the capacitor.

12. The embedded DRAM of claim 11, wherein the MOS capacitor has a junction leakage current that is decreased due to the N−

doped region.

13. The embedded DRAM of claim 11, wherein the MOS capacitor has a threshold voltage that is decreased due to the N−

doped region.

14. The embedded DRAM of claim 11, wherein the N−

doped region is fabricated at least in part by using an existing semiconductor mask.

15. The embedded DRAM of claim 11, further comprising a second P+ doped region in the N well.

16. The embedded DRAM of claim 15, further comprising a transfer gate over and between the P+ doped region and the second P+ doped region.

17. The embedded DRAM of claim 16, wherein the transfer gate has applied thereto a Vbb turn-on voltage to turn on the embedded DRAM and a Vpp turn-off voltage to turn off the embedded DRAM.

18. A method comprising:

fabricating a metal oxide semiconductor (MOS) capacitor of an embedded dynamic random access memory (DRAM) having a storage node formed between a P+ doped region and a polysilicon plate; and

,

N−

doping a region substantially completely under the polysilicon plate and substantially under the P+ doped region, to increase a retention time of the storage node of the capacitor.

19. The method of claim 18, wherein the MOS capacitor has a junction leakage current that is decreased due to the N−

doped region.

20. The method of claim 18, wherein the MOS capacitor has a threshold voltage that is decreased due to the N−

doped region.

21. The method of claim 18, wherein the N−

doped region is fabricated at least in part by using a semiconductor mask used in fabricating the MOS capacitor.