Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations

• US 6,847,248 B2
• Filed: 01/09/2002
• Issued: 01/25/2005
• Est. Priority Date: 01/09/2001
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US10/043,763
• Publication Number:
  US 20020175743A1
• Time in Patent Office: 1,112 Days
• Field of Search: 327/310, 327/313, 327/314, 327/320, 327/325, 327/328, 361/91.2, 361/91.5, 361/91.1
• US Class Current: 327/313
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

Claims

1. A method of protecting an integrated circuit from over voltage, the method comprising:

accepting a voltage from a power supply input to the integrated circuit;

accepting a pad voltage from an external voltage source;

comparing the power supply voltage to a predetermined value;

coupling a bias voltage for the integrated circuit to a gate of a PMOS (P-channel Metal Oxide Semiconductor) device when the power supply is below the predetermined value; and

coupling the pad voltage to a bias_mid node through the PMOS device to provide the bias voltage for the integrated circuit when the power supply is below the predetermined value,

wherein coupling the bias voltage for the integrated circuit to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device when the power supply is below the predetermined value comprises coupling the bias voltage to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device through a first plurality of diode connected MOS devices when the power supply is below the predetermined value.

2. A method of protecting an integrated circuit from over voltage, the method comprising:

accepting a voltage from a power supply input to the integrated circuit;

accepting a pad voltage from an external voltage source;

comparing the power supply voltage to a predetermined value;

coupling a bias voltage for the integrated circuit to a gate of a PMOS (P-channel Metal Oxide Semiconductor) device when the power supply is below the predetermined value; and

providing the pad voltage to an input of a plurality of diode connected MOS devices; and

coupling an output of the plurality of diode connected MOS devices to the drain of the PMOS device to couple the pad voltage to a bias_mid node to provide the bias voltage for the integrated circuit when the power supply is below the predetermined value.

6. The method of claim 2 further comprising:

providing V_DDO to a gate of a first semiconductor device providing the bias voltage for the integrated circuit to a source of the first semiconductor device such that the first semiconductor device will turn off when V_DDO minus the bias voltage for the integrated circuit is less than the threshold of the first semiconductor device; and

providing the bias voltage for the integrated circuit to the PMOS (P-channel Metal Oxide Semiconductor) device in response to the turn off of the first semiconductor device to couple the pad voltage to a bias_mid node to provide the bias voltage for the integrated circuit when the power supply is below the predetermined value.

7. The method of claim 2 wherein providing the bias voltage for the integrated circuit to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device in response to the turn off of the first semiconductor device to couple the pad voltage to a bias_mid node comprises:

turning on a second semiconductor device and turning off a third semiconductor device which is coupled to the second semiconductor device thereby providing the bias voltage for the integrated circuit to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device to turn on the PMOS (P-channel Metal Oxide Semiconductor) device; and

using the turn on of the PMOS (P-channel Metal Oxide Semiconductor) device to couple the pad voltage to a bias_mid node comprises.

8. The method of claim 7 wherein turning on a second semiconductor device and turning off a third semiconductor device comprises turning on a second semiconductor device, coupling the bias voltage for the integrated circuit to a gate of the third semiconductor device through a third plurality of diode connected MOS devices and the second semiconductor device to turn off the third semiconductor device.

9. The method of claim 2 wherein providing the bias voltage for the integrated circuit to the gate of the PMOS (P-channel Metal Oxide Semiconductor) device comprises providing the bias voltage for the integrated circuit to the gate of the PMOS (P-channel Metal Oxide Semiconductor) through a second plurality of diode connected MOS devices in response to the turn off of the first semiconductor device.

3. A method for generating a bias voltage (bias_mid) from a pad voltage (Vpad), when a power supply (V_DDO) is not present the method comprising:

providing V_DDO to a gate of a first semiconductor device;

providing bias_mid to a source of the first semiconductor device such that the first semiconductor device will turn off when V_DDO−

bias_mid is less than the threshold of the first semiconductor device; and

providing bias_mid to a gate of a MOS device in response to the turn off of the first semiconductor device to turn on the MOS device to couple Vpad to bias_mid,

wherein providing bias_mid to the gate of the MOS device in response to the turn off of the first semiconductor device to turn on the MOS device to couple Vpad to bias_mid comprises;

turning on a second semiconductor device and turning off a third semiconductor device which is coupled to the second semiconductor device thereby providing bias_mid to the gate of the MOS device to turn on the MOS device; and

using the turn on of the MOS device to couple Vpad to bias_mid, and

wherein using the turn on of the MOS device to couple Vpad to bias_mid comprises;

providing the pad voltage to an input of a first plurality of diode connected MOS devices; and

coupling an output of the first plurality of diode connected MOS devices to the drain of the MOS device.

4. A method for generating a bias voltage (bias_mid) from a pad voltage (Vpad), when a power supply (V_DDO) is not present the method comprising:

providing V_DDO to a gate of a first semiconductor device;

providing bias_mid to a source of the first semiconductor device such that the first semiconductor device will turn off when V_DDO−

bias_mid is less than the threshold of the first semiconductor device; and

providing bias_mid to a gate of a MOS device in response to the turn off of the first semiconductor device to turn on the MOS device to couple Vpad to bias_mid,

wherein providing bias_mid to the gate of the MOS device comprises providing bias_mid to the gate of the MOS device through a second plurality of diode connected MOS devices in response to the turn off of the first semiconductor device.

5. A method for generating a bias voltage (bias_mid) from a pad voltage (Vpad), when a power supply (V_DDO) is not present the method comprising:

providing V_DDO to a gate of a first semiconductor device;

providing bias_mid to a source of the first semiconductor device such that the first semiconductor device will turn off when V_DDO−

bias_mid is less than the threshold of the first semiconductor device; and

providing bias_mid to a gate of a MOS device in response to the turn off of the first semiconductor device to turn on the MOS device to couple Vpad to bias_mid,

wherein providing bias_mid to the gate of the MOS device in response to the turn off of the first semiconductor device to turn on the MOS device to couple Vpad to bias_mid comprises;

turning on a second semiconductor device and turning off a third semiconductor device which is coupled to the second semiconductor device thereby providing bias_mid to the gate of the MOS device to turn on the MOS device; and

using the turn on of the MOS device to couple Vpad to bias_mid, and

wherein turning on a second semiconductor device and turning off a third semiconductor device comprises turning on a second semiconductor device, coupling Vpad to a gate of the third semiconductor device through a third plurality of diode connected MOS devices and the second semiconductor device to turn off the third semiconductor device.

10. A method of protecting an integrated circuit from over voltage, the method comprising:

accepting a voltage from a power supply input to the integrated circuit;

accepting a pad voltage via a pad from an external voltage source to the integrated circuit; and

if the power supply voltage has a first value less than a predetermined value;

turning off a first switch disposed between the pad and a gate terminal of a second switch disposed between the pad and a bias node; and

turning on a third switch disposed between the bias node and the gate terminal of the second switch,

thereby turning on the second switch to provide a bias voltage for the integrated circuit at the bias node;

wherein the pad voltage is applied at the bias node as the bias voltage through a plurality of diode connected transistors and the second switch.

14. The method of claim 10, further comprising:

if the power supply voltage has a second value greater than the predetermined value, turning off the second switch, such that the pad voltage is not provided to the bias node through the second switch.

11. A method of protecting an integrated circuit from over voltage, the method comprising:

accepting a voltage from a power supply input to the integrated circuit;

accepting a pad voltage via a pad from an external voltage source to the integrated circuit; and

if the power supply voltage has a first value less than a predetermined value;

turning off a first switch disposed between the pad and a gate terminal of a second switch disposed between the pad and a bias node; and

turning on a third switch disposed between the bias node and the gate terminal of the second switch,

thereby turning on the second switch to provide a bias voltage for the integrated circuit at the bias node;

wherein said turning off the first switch comprises applying the pad voltage at a gate terminal of the first switch through a plurality of diode connected transistors.

12. The method of claim 11, wherein said applying the pad voltage comprises turning on a fourth switch disposed between the gate terminal of the first switch and the pad voltage.

13. A method of protecting an integrated circuit from over voltage, the method comprising:

accepting a voltage from a power supply input to the integrated circuit;

accepting a pad voltage via a pad from an external voltage source to the integrated circuit; and

if the power supply voltage has a first value less than a predetermined value;

turning off a first switch disposed between the pad and a gate terminal of a second switch disposed between the pad and a bias node; and

turning on a third switch disposed between the bias node and the gate terminal of the second switch,

thereby turning on the second switch to provide a bias voltage for the integrated circuit at the bias node;

wherein the third switch is coupled to the gate terminal of the second switch through a plurality of diode connected transistors.