Closed loop amplification with high throughput performance
First Claim
Patent Images
1. An integrated circuit comprising:
- a closed loop amplifier circuit containing an operational amplifier with a finite gain; and
a correction circuit correcting an error In an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error.
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Abstract
Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed loop amplifier using an operational amplifier with infinite gain) that would result from the use of the operational amplifier with low gain. In an embodiment implemented in relation to an analog to digital converter (ADC), a mathematical operation is performed on the digital code(s) generated by the ADC to generate a corrected code corresponding to an analog sample.
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Citations
19 Claims
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1. An integrated circuit comprising:
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a closed loop amplifier circuit containing an operational amplifier with a finite gain; and
a correction circuit correcting an error In an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error. - View Dependent Claims (2, 3)
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4. An integrated circuit comprising:
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a closed loop amplifier circuit containing an operational amplifier with a finite gain; and
a correction circuit correcting an error in an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error, and wherein said first ratio equals ((F−
1) (1+factor)), wherein F equals the desired amplification factor for said closed loop amplifier circuit and said factor equals ((1/A1+1/A2)×
(1+Z1/Z2)/2), wherein said finite gain varies between A1 and A2.
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5. An integrated circuit comprising:
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a closed loop amplifier circuit containing an operational amplifier with a finite gain; and
a correction circuit correcting an error in an output of said closed loop amplifier, wherein said closed loop amplifier circuit receives an analog input signal and generates an analog output signal as said output, said integrated circuit further comprising;
an analog to digital converter (ADC) converting a sample of said analog output signal to an Intermediate digital code, wherein said correction circuit corrects said error by performing a mathematical operation on said intermediate digital code to generate a corrected digital code representing said output corrected for said error, and wherein said intermediate digital code comprises a plurality of sub-codes (V1, V2, . . . Vn) generated by a corresponding plurality of sub-ADCs contained in said ADC, wherein said closed loop amplifier circuit is contained in a first stage generating said V1, said mathematical operation comprises;
multiplying a value formed by (V2, . . . Vn) by (1+Factor), wherein Factor equals (F/A), A equals sad finite gain.
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6. An analog to digital converter (ADC) converting a sample of an analog signal to a digital code, said ADC comprising:
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a plurality of stages, each of said plurality of stages generating a corresponding one of a plurality of sub-codes, each of said plurality of sub-codes containing at least one bit wherein said sub-codes are used to generate said digital code, at least one of said plurality of stages comprising;
a sub-ADC receiving an input signal and generating a corresponding one of said plurality of sub-codes representing a strength of said input signal;
a digital to analog converter (DAC) converting said corresponding one of said plurality of sub-codes to a corresponding intermediate signal;
an subtractor subtracting a said corresponding intermediate signal from said input signal to generate an subtractor output; and
a closed loop amplifier containing an operational amplifier with a finite gain, said closed loop amplifier amplifying said subtractor output to generate said input signal for a next stage; and
a correction circuit correcting an error in an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance having impedance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error. - View Dependent Claims (7, 8, 9, 10)
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11. An analog to digital converter (ADC) converting a sample of an analog signal to a digital code, said ADC comprising:
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a plurality of stages, each of said plurality of stages generating a corresponding one of a plurality of sub-codes, each of said plurality of sub-codes containing at least one bit, wherein said sub-codes are used to generate said digital code, at least one of said plurality of stages comprising;
a sub-ADC receiving an input signal and generating a corresponding one of said plurality of sub-codes representing a strength of said input signal;
a digital to analog converter (DAC) converting said corresponding one of said plurality of sub-codes to a corresponding intermediate signal;
an subtractor subtracting said corresponding intermediate signal from said input signal to generate an subtractor output; and
a closed loop amplifier containing an operational amplifier with a finite gain, said closed loop amplifier amplifying said subtractor output to generate said input signal for a next stage; and
a correction circuit correcting an error in an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance having impedance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error, and wherein said first ratio equals ((F−
1) (1+factor)), wherein F equals the desired amplification factor for said closed loop amplifier circuit and said factor equals ((1/A1+1/A2)×
(1+Z1/Z2)/2), wherein said finite gain varies between A1 and A2.
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12. A device comprising:
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an analog to digital converter (ADC) converting a sample of an analog signal to a digital code, said ADC comprising;
a plurality of stages, each of said plurality of stages generating a corresponding one of a plurality of sub-codes, each of said plurality of sub-codes containing at least one bit, at least one of said plurality of stages comprising;
a sub-ADC receiving an input signal and generating a corresponding one of said plurality of sub-codes representing a strength of said input signal;
a digital to analog converter (DAC) converting said corresponding one of said plurality of sub-codes to a corresponding intermediate signal;
an subtractor subtracting said corresponding intermediate signal from said input signal to generate an subtractor output; and
a closed loop amplifier containing an operational amplifier with a finite gain, said closed loop amplifier amplifying said subtractor output to generate said input signal for a next stage;
a correction circuit correcting an error In an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance having resistance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error. - View Dependent Claims (13, 14, 15, 16, 17)
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18. The device of claim a 12, wherein said device comprises a wireless base station.
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19. A device comprising:
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an analog to digital converter (ADC) converting a sample of an analog signal to a digital code, said ADC comprising;
a plurality of stages, each of said plurality of stages generating a corresponding one of a plurality of sub-codes, each of said plurality of sub-codes containing at least one bit, at least one of said plurality of stages comprising;
a sub-ADC receiving an input signal and generating a corresponding one of said plurality of sub-codes representing a strength of said input signal;
a digital to analog converter (DAC) converting said corresponding one of said plurality of sub-codes to a corresponding intermediate signal;
an subtractor subtracting said corresponding intermediate signal from said input signal to generate an subtractor output; and
a closed loop amplifier containing an operational amplifier with a finite gain, said closed loop amplifier amplifying said subtractor output to generate said input signal for a next stage;
a correction circuit correcting an error in an output of said closed loop amplifier, wherein said correction circuit comprises a feedback impedance and an reference impedance having resistance of a first ratio, wherein said first ratio is determined by adjusting a desired amplification factor according to said error, and wherein said first ratio equals ((F-1) (1+factor)), wherein F equals the desired amplification factor for said closed loop amplifier circuit and said factor equals ((1/A1+1 A2)×
(1+Z1/Z2)/2), wherein said finite gain varies between A1 and A2.
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Specification