Column address path circuit and method for memory devices having a burst access mode

• US 6,848,040 B2
• Filed: 04/15/2003
• Issued: 01/25/2005
• Est. Priority Date: 03/09/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ho, Duc V.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US10/414,818
• Publication Number:
  US 20040013010A1
• Time in Patent Office: 651 Days
• Field of Search: 711217-220, 711/104, 711/105, 711/147, 711/150, 711/154, 711/163, 711/167, 711/168, 710/35, 710/52, 710/58
• US Class Current: 711/217
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address. The adder logic circuit processes the column address bits at the same time the address bits are being coupled through the second multiplexer to the first multiplexer as a function of the correct relationship between the internal address bits and the external address bits.

Claims

1. A system for generating an internal address bit, comprising:

an inverter circuit receiving first external address bit and generating the complement of the first external address bit;

a selection circuit coupled to the inverter circuit, the selection circuit receiving the first external address bit and the complement of the first external address bit, the selection circuit coupling one of the first external address bit and the complement of the first external address bit to an output terminal to generate a first internal address bit responsive to a control signal applied to a control terminal of the selection circuit; and

a logic circuit receiving a second external address bit, the logic circuit being coupled to the control terminal of the selection circuit, the logic circuit generating the control signal as a function of the second external address bit.

2. The system of claim 1 wherein the first external address bit comprises an external column address bit, and the first internal address bit comprises an internal column address bit.

3. The system of claim 1, further comprising a latch coupled to receive the first and second external address bits, the latch storing the first and second external address bits prior to coupling the first and second external address bits to the selection circuit and the logic circuit, respectively.

4. The system of claim 1 wherein the selection circuit comprises a multiplexer.

5. The system of claim 1, further comprising:

a counter having a counter output; and

a multiplexer having a first input coupled to receive the first external address bit, a second input coupled to the inverter circuit to receive the complement of the first external address bit, a third input coupled to the counter output, and at least one multiplexer output coupled to the selection circuit, the multiplexer being operable to couple either the third input to the selection circuit or the first and second inputs to the selection circuit responsive to a second control signal.

6. The system of claim 5 wherein the second control signal is operable to cause the multiplexer to couple the third input to the selection circuit during a first bit of an address burst, and to cause the multiplexer to couple the first and second inputs to the selection circuit during subsequent bits of an address burst.

7. The system of claim 1 wherein the first external address bit is identical to the second external address bit.

8. The system of claim 1 wherein the first address bit is different from the second external address bit.

9. The system of claim 1 wherein the logic circuit is operable to generate the control signal as a function of the first external address bit and the second external address bit.

10. A memory device, comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;

a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;

a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address; and

a burst controller coupled to the address bus and to one of the address circuits, the burst controller comprising;

an inverter circuit receiving first external address bit am the address bus and generating the complement of the first external address bit;

a selection circuit coupled to the inverter circuit, the selection circuit receiving the first external address bit and the complement of the first external address bit, the selection circuit coupling one of the first external address bit and the complement of the first external address bit to an output terminal to generate an internal address bit responsive to a control signal applied to a control terminal of the selection circuit; and

a logic circuit receiving a second external address bit, the logic circuit being coupled to the control terminal of the selection circuit, the logic circuit generating the control signal as a function of the second external address bit.

11. The memory device of claim 10 wherein the first external address bit comprises an external column address bit, and the first internal address bit comprises an internal column address bit.

12. The memory device of claim 10, further comprising a latch coupled to receive the first and second external address bits, the latch at storing the first and second external address bits prior to coupling the first and second external address bits to the selection circuit and the logic circuit, respectively.

13. The memory device of claim 10 wherein the selection circuit comprises a multiplexer.

14. The memory device of claim 10, further comprising:

a counter having a counter output; and

a multiplexer having a first input coupled to receive the first external address bit, a second input coupled to the inverter circuit to receive the complement of the first external address bit, a third input coupled to the counter output, and at leas one multiplexer output coupled to the selection circuit, the multiplexer being operable to couple either the third input to the selection circuit or the first and second inputs to the selection circuit responsive to a second control signal.

15. The memory device of claim 14 wherein the second control signal is operable to cause the multiplexer to couple the third input to the selection circuit during a first bit of an address burst, and to cause the multiplexer to couple the first and second inputs to the selection circuit during subsequent bits of an address burst.

16. The memory device of claim 10 wherein the first external address bit is identical to the second external address bit.

17. The memory device of claim 10 wherein the first external address bit is different from the second external address bit.

18. The memory device of claim 10 wherein the logic circuit is operable to generate the control signal as a function of the first external address bit and the second external address bit.

19. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising;

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;

a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;

a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address; and

a burst controller coupled to the address bus and to one of the address circuits, the burst controller comprising;

an inverter circuit receiving first external address bit from the address bus and generating the complement of the first external address bit;

a selection circuit coupled to the inverter circuit, the selection circuit receiving the first external address bit and the complement of the first external address bit, the selection circuit coupling one of the first external address bit and the complement of the first external address bit to an output terminal to generate a first internal address bit responsive to a control signal applied to a control terminal of the selection circuit; and

a logic circuit receiving the external address bit, the logic circuit being coupled to the control terminal of the selection circuit, the logic circuit generating the control signal as a function of a second external address bit.

20. The computer system of claim 19 wherein the first external address bit comprises an external column address bit, and the first internal address bit comprises an internal column address bit.

21. The computer system of claim 19, further comprising a latch coupled to receive the first and second external address bits, the latch storing the first and second external address bits prior to coupling the first and second external address bits to the selection circuit and the logic circuit, respectively.

22. The computer system of claim 19 wherein the selection circuit comprises a multiplexer.

23. The computer system of claim 19, further comprising:

a counter having a counter output; and

a multiplexer having a first input coupled to receive the first external address bit, a second input coupled to the inverter circuit to receive the complement of the first external address bit, a third input coupled to the counter output, and at least one multiplexer output coupled to the selection circuit, the multiplexer being operable to couple either the third input to the selection circuit or the first and second inputs to the selection circuit responsive to a second control signal.

24. The computer system of claim 23 wherein the second control signal is operable to cause the multiplexer to couple the third input to the selection circuit during a first bit of an address burst, and to cause the multiplexer to couple the first and second inputs to the selection circuit during subsequent bits of an address burst.

25. The computer system of claim 19 wherein the first external address bit is identical to the second external address bit.

26. The computer system of claim 19 wherein the first external address bit is different from the second external address bit.

27. The computer system of claim 19 wherein the logic circuit is operable to generate the control signal as a function of the first external address bit and the second external address bit.

28. A method of generating a bit of internal address, the method comprising:

receiving a bit of first external address;

generating a complement of the bit of the first external address;

coupling the bit of the first external address and the complement of the bit of the first external address through a first signal path;

while the first external address bit and the complement of the bit of the first external address are being coupled through the first signal path, examining a second external address bit; and

selecting as an internal address bit either the bit of the first external address or the complement of the bit of the first external address based on the examination.

29. The method of claim 28 wherein the first external address bit comprises an external column address bit, and the first internal address bit comprises an internal column address bit.

30. The method of claim 28 wherein the act of examining the second external address bit comprises examining the second external address bit to determine the relationship between the second external address bit and first the internal column address bit.

31. The method of claim 28, wherein the act of coupling a bit of the first external address and its complement through the first signal path comprises:

providing an incrementally increasing address; and

selecting either a bit of the incrementally increasing address or the first external address and the complement of the first external address for coupling through the first signal path.

32. The method of claim 28 wherein the first external address bit is identical to the second external address bit.

33. The method of claim 28 wherein the first external address bit is different from the second external address bit.

34. The method of claim 28 wherein the act of selecting as an internal address bit either the bit of the first external address or the complement of the bit of the first external address based on the examination of the second external address bit further comprises selecting the internal address bit based on an examination of the first external address bit.

35. A method of generating a bit of an internal address bit, comprising:

processing a first external address bit;

coupling a bit of the first external address and its complement through a first signal path while a second external address bit is being processed; and

selecting either the bit of the first external address or its complement as the internal address bit based on the processing of the second external address bit.

36. The method of claim 35 wherein the first internal address bit comprises an internal column address bit, and wherein the first external address bit comprises an external column address bit.

37. The method of claim 35 wherein the act of processing the second external address bit comprises processing the second external address bit to determine the relationship between the first internal address bit and the second external address bit.

38. The method of claim 37 wherein the act of processing the second external address bit to determine the relationship between the first internal address bit and the second external address bit further comprises processing the second external address bit in one manner responsive to operation in one mode and processing the second external address bit in a different manner responsive to operation in a different mode.

39. The method of claim 35 wherein the act of coupling a bit of the first external address and its complement through a first signal path comprises:

receiving and storing the first external address bit;

inverting the stored first external address bit;

coupling the stored first external address bit through the first signal path; and

coupling the inverted stored first external address bit through the first signal path.

40. The method of claim 35 wherein the act of coupling a bit of the first external address and its complement through the first signal path comprises:

applying a bit of a counter to a first input of a multiplexer placed in the first signal path,

applying a bit of the first external address and its complement to respective second inputs of the multiplexer; and

coupling either the first input or the second inputs of the multiplexer through the first signal path.

41. The method of claim 35 wherein the first external address bit is identical to the second external address bit.

42. The method of claim 35 wherein the first external address bit is different from the second external address bit.

43. The method of claim 35 further comprising:

processing the first external address bit; and

selecting either the bit of the first external address or its complement as the internal address bit based on the processing of both the first external address bit and processing of the second external address bit.