Synchronous to asynchronous to synchronous interface

• US 6,848,060 B2
• Filed: 02/27/2001
• Issued: 01/25/2005
• Est. Priority Date: 02/27/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schuster, Stanley E., Cook, Peter W.
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): Trujillo, James K.
• Application Number:
  US09/794,467
• Publication Number:
  US 20020120883A1
• Time in Patent Office: 1,428 Days
• Field of Search: 713/400, 713/401, 713/500, 713/502, 713/503, 713/600, 713/601, 713/300, 713/323, 713/324, 326/93, 326/98, 326/95, 710/52, 710/58, 710/61
• US Class Current: 713/400
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages

Abstract

An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Claims

1. An interface between synchronous and asynchronous data transfer, comprising:

a plurality of stages coupled to each other to form a pipeline for data transfer;

the plurality of stages including;

a first stage which performs synchronous to asynchronous data transfer;

at least one intermediate stage which performs asynchronous to asynchronous data transfer; and

a last stage which performs asynchronous to synchronous data transfer; and

a synchronous clock path which propagates a timing signal across the plurality of stages in response to a synchrounous clock signal to enable the first and last stages to perform operations when the timing signal is present at that stage.

2. The interface as recited in claim 1, wherein the first and last stages includes a local clock circuit, the local clock circuit includes an AND gate to AND the timing signal and the synchronous clock signal.

3. The interface as recited in claim 2, wherein the timing signal is propagated by a one bit wide synchronous register.

4. The interface as recited in claim 2, wherein the local clock circuit corresponding to the first stage further comprises a precharge circuit coupled to the first stage wherein the precharge circuit generates a precharge pulse when a handshaking acknowledgment is received from the at least one intermediate stage that data has been received.

5. The interface as recited in claim 4, wherein the local clock circuit corresponding to the first stage further comprises a valid data signal generated when a local clock signal transitions and resets when the precharge pulse transitions, the valid data signal being sent to the at least one intermediate stage to indicate that valid data is available.

6. The interface as recited in claim 2, wherein the local clock circuit corresponding to the last stage further comprises a precharge circuit coupled to the last stage wherein the precharge circuit generates a precharge pulse and an acknowledge pulse that is initiated by the synchronous clock transitioning and terminated by the local clock signal transitioning for the last stage.

7. The interface as recited in claim 2, wherein the local clock circuit corresponding to the last stage further comprises an error signal generated if the local clock and a valid data signal from the at least one intermediate stage indicate that data is invalid.

8. The interface as recited in claim 1, where the at least one intermediate stage includes a plurality of stages which are pipelined and interlocked in the forward and reverse directions.

9. A synchronous to asynchronous to synchronous interface, comprising:

a plurality of stages coupled to each other to form a pipeline;

the plurality of stages including;

a first stage which performs synchronous to asynchronous data transfer;

at least one intermediate stage which performs asynchronous to asynchronous data transfer; and

a last stage which performs asynchronous to synchronous data transfer;

a clock circuit coupled to each of the plurality of stages which generates a local clock signal for the first and the last stages based on a synchronous clock signal and provides interlocking operation signals with stages interacting with the at least one intermediate stage, the local clock signal enabling the first stage and the last stage when an operation is to be performed by that corresponding stage.

10. The interface as recited in claim 9, wherein the clock circuit first and last stages includes an AND gate to AND a timing signal, indicating that an operation is to be performed, and the synchronous clock.

11. The interface as recited in claim 10, wherein the timing bit is propagated by a one bit wide synchronous register.

12. The interface as recited in claim 9, wherein the clock circuit corresponding to the first stage further comprises a precharge circuit coupled to the first stage wherein the precharge circuit generates a precharge pulse when a handshaking acknowledgment is received from the at least one intermediate stage that data has been received.

13. The interface as recited in claim 12, wherein the clock circuit corresponding to the first stage further comprises a valid data signal generated when the local clock signal transitions and resets when the precharge pulse transitions, the valid data signal being sent to the at least one intermediate stage to indicate that valid data is available.

14. The interface as recited in claim 9, wherein the clock circuit corresponding to the last stage further comprises a precharge circuit coupled to the last stage wherein the precharge circuit generates a precharge pulse and an acknowledge pulse that is initiated by the synchronous clock transitioning and terminated by the local clock signal transitioning for the last stage.

15. The interface as recited in claim 14, wherein the clock circuit corresponding to the last stage further comprises an error signal generated if the local clock and a valid data signal from the at least one intermediate stage indicate that data is invalid.

16. The interface as recited in claim 9, where the at least one intermediate stage includes a plurality of stages which are pipelined and interlocked in the forward and reverse directions.

17. A method for synchronous to asynchronous to synchronous data transfer, comprising the steps of:

providing a plurality of stages coupled to each other to form a pipeline, the plurality of stages including a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer;

propagating a synchronous timing signal along a synchronous clock path in response to a synchronous clock signal; and

enabling one of the first stage and the last stage of the plurality of stages only when an operation is to be performed to permit data transfer, the first and last stages being enabled by local clock signals generated by a clock circuit included at each of the plurality of stages, the local clock signal being generated in response to the synchronous clock signal and timing signal.

18. The method as recited in claim 17, wherein the clock circuit of the first and last stages includes an AND gate and further comprising the step of ANDing the timing signal, indicating that an operation is to be performed, and the synchronous clock.

19. The method as recited in claim 17, further comprising the step of propagating the timing signal by a one bit wide synchronous register.

20. The method as recited in claim 17, wherein the clock circuit corresponding to the first stage further comprises a precharge circuit coupled to the first stage and further comprising the step of generating a precharge pulse when a handshaking acknowledgment is received from the at least one intermediate stage that data has been received.

21. The method as recited in claim 20, wherein the clock circuit corresponding to the first stage further comprises a valid data signal generated when the local clock signal transitions and resets when the precharge pulse transitions, and further comprising the step of sending the valid data signal to the at least one intermediate stage to indicate that valid data is available.

22. The method as recited in claim 17, the clock circuit corresponding to the last stage further comprises a precharge circuit coupled to the last stage and further comprising the step of generating a precharge pulse that is initiated by the synchronous clock transitioning and terminated by the local clock signal transitioning.

23. The method as recited in claim 17, wherein the clock circuit corresponding to the last stage provides an error signal, and further comprising the step of generating the error signal if the local clock signal and a valid data signal from the at least one intermediate stage indicates that data is invalid.

24. A synchronous clock gating interface, comprising:

a plurality of synchronous stages coupled to each other to form a pipeline;

a plurality of clock circuits coupled to each other to form a synchronous clock path, wherein each clock circuit is coupled to a corresponding one of the plurality of stages, wherein each clock circuit generates a local clock signal for a corresponding stage based on a synchronous clock signal and a timing signal wherein the local clock signal enables the corresponding stage when an operation is to be performed by the corresponding stage.

25. The interface as recited in claim 24, wherein each clock circuit includes an AND gate to AND the timing signal, indicating that an operation is to be performed, and the synchronous clock.

26. The interface as recited in claim 24, wherein the timing signal is propagated by a one bit wide synchronous register.