Thin layer metal chemical vapor deposition

• US 6,849,122 B1
• Filed: 03/07/2002
• Issued: 02/01/2005
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Fair, James A.
• Primary Examiner(s): KUNEMUND, ROBERT M
• Application Number:
  US10/094,308
• Time in Patent Office: 1,062 Days
• Field of Search: 117/89, 117/104, 117/102, 117/937
• US Class Current: 117/89
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/02 Elements
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76873 for electroplating

Abstract

A CVD method deposits conformal metal layers on small features of a substrate surface. The method includes three principal operations: depositing a thin conformal layer of precursor over some or all of the substrate surface; oxidizing the precursor to convert it to a conformal layer of metal oxide; and reducing some or all of the metal oxide to convert it to a conformal layer of the metal itself. The conformal layer of precursor may form a “monolayer” on the substrate surface. Examples of metals for deposition include copper, cobalt, ruthenium, indium, and rhodium.

Claims

1. A method of forming a metal layer on a workpiece, the method comprising

(a) depositing a layer of organo-metallic precursor on a surface of the workpiece;

(b) oxidizing the organo-metallic precursor to form a metal oxide layer on the surface; and

(c) reducing at least a portion of the metal oxide layer to form the metal layer on the workpiece.

2. The method of claim 1, wherein (a) is performed on an exposed layer of diffusion barrier on the workpiece, an exposed adhesion layer on the workpiece, or an exposed dielectric layer on the workpiece.

3. The method of claim 1 wherein the workpiece is a partially fabricated integrated circuit having one or more gaps, and wherein the surface of the partially fabricated integrated circuit surface comprises features having an aspect ratio of at least about 5:

1.

4. The method of claim 3 wherein the features have a principal dimension at most about 0.26 μ

m.

5. The method of claim 3, further comprising electro-depositing a bulk layer of metal on the partially fabricated integrated circuit to thereby fill the gaps with the metal.

6. The method of claim 5, wherein the bulk layer of metal forms conductive lines on the integrated circuit.

7. The method of claim 3 further comprising depositing a second metal layer on the metal layer, wherein the metal layer helps the second metal layer to adhere to the surface of the partially fabricated integrated circuit.

8. The method of claim 1, wherein the metal is copper, cobalt, ruthenium, rhodium, indium, or a combination thereof.

9. The method of claim 1, wherein the organo-metallic precursor comprises an organo-copper compound, an organo-cobalt compound, an organo-ruthenium compound, an organo-iridium compound, an organo-rhodium compound, or a combination thereof.

10. The method of claim 1, wherein (a) comprises absorbing a layer of the organo-metallic precursor the surface of the workpiece.

11. The method of claim 1, wherein (a) comprises forming a saturated layer of the organo-metallic precursor on the surface of the workpiece.

12. The method of claim 1, wherein (a) comprises depositing a layer of the organo-metallic precursor on the surface of the workpiece by atomic layer chemical vapor deposition.

13. The method of claim 1, wherein (b) comprises oxidizing the organo-metallic precursor layer with an oxygen plasma or an oxygen-containing plasma.

14. The method of claim 1, wherein (c) comprises reducing the metal oxide layer with a hydrogen plasma or a hydrogen-containing plasma.

15. A method of depositing a thin layer of cobalt metal on a substrate surface, the method comprising

(a) depositing a layer of organo-cobalt precursor on a surface of the substrate;

(b) oxidizing the organo-cobalt precursor to form a cobalt oxide layer on the surface; and

(c) reducing at least a portion of the cobalt oxide layer to form the cobalt layer on the substrate surface.

16. The method of claim 15, wherein the substrate is a partially fabricated integrated circuit.

17. The method of claim 15, wherein (a) is performed on an exposed layer of diffusion barrier on the substrate surface.

18. The method of claim 15, wherein the organo-cobalt precursor comprises cobalt carbonyl (Co₂(CO)₆), cobaltocene (Co(C₅H₅)₂), cyclopentadienyl cobalt dicarbonyl (C₅H₅Co(CO)₂), cobalt acetylacetonate (Co(C₅H₇O₂)₃), cobalt tricarbonyl nitrosyl (Co(CO)₃NO) or a combination thereof.

19. The method of claim 15, wherein (a) comprises absorbing a layer of the organo-cobalt precursor the substrate surface.

20. The method of claim 15, wherein (a) comprises forming a saturated layer of the organo-cobalt precursor on the substrate surface.

21. The method of claim 15, wherein (a) comprises depositing a layer of the organo-cobalt precursor on the substrate surface by atomic layer chemical vapor deposition.

22. The method of claim 15, wherein (b) comprises oxidizing the organo-cobalt precursor layer with an oxygen plasma or an oxygen-containing plasma.

23. The method of claim 15, wherein (c) comprises reducing the cobalt oxide layer with a hydrogen plasma or a hydrogen-containing plasma.

24. The method of claim 15, further comprising depositing a seed layer of copper on the cobalt layer.

25. The method of claim 24, further comprising electro-depositing a bulk layer of copper on the substrate to thereby fill gaps on the substrate surface with copper.

26. The method of claim 25, wherein the bulk layer of copper forms conductive lines on an integrated circuit.