RRAM memory cell electrodes

• US 6,849,891 B1
• Filed: 12/08/2003
• Issued: 02/01/2005
• Est. Priority Date: 12/08/2003
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Zhang, Fengyan, Hsu, Sheng Teng, Li, Tingkai, Pan, Wei, Zhuang, Wei-Wei
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R.
• Application Number:
  US10/730,584
• Time in Patent Office: 421 Days
• Field of Search: 257/44, 257/192, 257/296, 257/310, 360/324, 360/326
• US Class Current: 257/296
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.

Claims

1. A RRAM memory cell formed on a silicon substrate having a operative junction formed therein and a metal plug formed on the operative junction, comprising:

a stack of the following layers, wherein each layer has the same horizontally disposed size as an immediately underlying layer;

a first oxidation resistive layer formed on the metal plug;

a first refractory metal layer formed on the oxidation resistive layer;

a CMR layer formed on the first refractory metal layer;

a second refractory metal layer formed on the CMR layer; and

a second oxidation resistive layer formed on the second refractory metal layer;

wherein “

on”

means directly on without any intervening structures.

2. The RRAM memory cell of claim 1 wherein the oxidation resistive layer are formed of a material taken from the group of materials consisting of TiN, TaN, TiAlN_x, TaAlN_x, TaSiN, TiSiN, and RuTiN.

3. The RRAM memory cell of claim 2 wherein the oxidation resistive layers have a thickness of between about 50 nm to 300 nm.

4. The RRAM memory cell of claim 1 wherein the refractory metal layers are formed of a material taken from the group of materials consisting of Pt, Ir, IrO₂, Ru, RuO₂, Au, Ag, Rh, Pd, Ni, and Co.

5. The RRAM memory cell of claim 4 wherein the refractory metal layers have a thickness of between about 3 nm to 50 nm.

6. The RAM memory cell of claim 1 wherein the CMR layer is formed of a material taken from the group of material consisting of CMR materials and high-temperature superconductors.

7. The RRAM memory cell of claim 6 wherein the CMR layer has a thickness of between about 50 nm to 300 nm.

8. A method of fabricating a multi-layer electrode RRAM memory cell comprising:

preparing a silicon substrate;

forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions;

depositing a metal plug on the junction;

depositing a first oxidation resistant layer on the metal plug;

depositing a first refractory metal layer on the first oxidation resistant layer;

depositing a CMR layer on the first refractory metal layer;

depositing a second refractory metal layer on the CMR layer;

depositing a second oxidation resistant layer on the second refractory metal layer; and

completing the RRAM memory cell.

9. The method of claim 8 wherein said depositing the oxidation resistive layers includes depositing a material taken from the group of materials consisting of TiN, TaN, TiAlN_x, TaAlN_x, TaSiN, TiSiN, and RuTiN.

10. The method of claim 9 wherein said depositing the oxidation resistive layers includes depositing the oxidation resistive layers to a thickness of between about 50 nm to 300 nm.

11. The method of claim 8 wherein said depositing the refractory metal layers includes depositing a material taken from the group of materials consisting of Pt, Ir, IrO₂, Ru, RuO₂, Au, Ag, Rh, Pd, Ni, and Co.

12. The method of claim 11 wherein said depositing the refractory metal layers includes depositing the refractory metal to a thickness of between about 3 nm to 50 nm.

13. The method of claim 8 wherein said depositing a CMR layer includes depositing a layer of CMR material taken from the group of material consisting of PCMO, LPCMO and high-temperature superconductors.

14. The method of 13 wherein said depositing a CMR layer includes depositing a layer of CMR material having a thickness of between about 50 nm to 300 nm.