Trench MIS device with active trench corners and thick bottom oxide

• US 6,849,898 B2
• Filed: 08/10/2001
• Issued: 02/01/2005
• Est. Priority Date: 08/10/2001
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Terrill, Kyle, Chen, Kuo-In, Darwish, Mohamed N., Lui, Kam Hong, Giles, Frederick P.
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/927,143
• Publication Number:
  US 20030032247A1
• Time in Patent Office: 1,271 Days
• Field of Search: 257/330, 257/327, 257/328, 257/329
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

Trench MOSFETs including active corner regions and a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such MOSFETs. In an exemplary embodiment, the trench MOSFET includes a thick insulative layer centrally located at the bottom of the trench. A thin gate insulative layer lines the sidewall and a peripheral portion of the bottom surface of the trench. A gate fills the trench, adjacent to the gate insulative layer. The gate is adjacent to the sides and top of the thick insulative layer. The thick insulative layer separates the gate from the drain conductive region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications.

Claims

1. A metal-insulator-semiconductor device, comprising:

a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;

a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;

a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall and to a first portion of a bottom surface of said trench; and

a drain region of said first conductivity type adjacent to said body region and to a second portion of said bottom surface of said trench,

wherein said trench is lined with a first insulative layer at least along said sidewall that abuts said body region and at least along said first portion of said bottom surface that abuts said body region, and wherein said trench is lined with a second insulative layer at least along said second portion of said bottom surface of said trench, said second insulative layer being coupled to said first insulative layer and said second insulative layer being thicker than said first insulative layer.

2. The MIS device of claim 1, further comprising a gate region coupled to said first insulative layer and said second insulative layer within said trench.

3. The MIS device of claim 2, wherein said gate region comprises polysilicon.

4. The MIS device of claim 1, further including a high conductivity region of said first conductivity type formed in said drain region adjacent to at least said second portion of said bottom surface of said trench.

5. The MIS device of claim 1, wherein said first insulative layer extends to the interface between said first portion of said bottom surface and said second portion of said bottom surface.

6. The MIS device of claim 5, wherein said body region extends to the interface between said first portion of said bottom surface and said second portion of said bottom surface.

7. The MIS device of claim 5, wherein said body region extends to a first distance along said first portion of said bottom surface of said trench.

8. The MIS device of claim 1, wherein said first insulative layer comprises an oxide.

9. The MIS device of claim 1, wherein said second insulative layer comprises an oxide.

10. The MIS device of claim 1, wherein said second insulative layer comprises a multi-layer insulative layer.

11. The MIS device of claim 1, wherein said MIS device comprises a MOSFET.

12. A trench-gated MOSFET, comprising:

a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;

a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;

a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall and to a peripheral portion of a bottom surface of said trench;

a drain region of said first conductivity type adjacent to said body region and to a central portion of said bottom surface of said trench,

wherein said trench is lined with a first insulative layer at least along said sidewall that abuts said body region and at least along said peripheral portion of said bottom surface that abuts said body region, and wherein said trench is lined with a second insulative layer at least along said central portion of said bottom surface of said trench, said second insulative layer being coupled to said first insulative layer and said second insulative layer being thicker than said first insulative layer; and

a gate region coupled to said first insulative layer and said second insulative layer within said trench.

13. The trench-gated MOSFET of claim 12, wherein said gate region comprises polysilicon.

14. The trench-gated MOSFET of claim 12, further including a high conductivity region of said first conductivity type formed in said drain region adjacent to at least said central portion of said bottom surface of said trench.

15. The trench-gated MOSFET of claim 12, wherein said first insulative layer extends to the interface between said peripheral portion of said bottom surface and said central portion of said bottom surface.

16. The trench-gated MOSFET of claim 15, wherein said body region extends to the interface between said peripheral portion of said bottom surface and said central portion of said bottom surface.

17. The trench-gated MOSFET of claim 15, wherein said body region extends to a first distance along said peripheral portion of said bottom surface of said trench.

18. The trench-gated MOSFET of claim 12, wherein said first insulative layer comprises an oxide.

19. The trench-gated MOSFET of claim 12, wherein said second insulative layer comprises an oxide.

20. The trench-gated MOSFET of claim 12, wherein said second insulative layer comprises multi-layer insulative layer.

21. A trench-gated MOSFET, comprising:

a semiconductor substrate including a trench extending into said substrate from a first surface of said substrate, said trench including a sidewall, a corner surface, and a central bottom surface;

a source region of a first conductivity type adjacent to said sidewall of said trench and to said first surface;

a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall and to said corner surface of said trench;

a drain region of said first conductivity type adjacent to said body region and to said central bottom surface of said trench,

wherein said trench is lined with a first insulative layer at least along said sidewall that abuts said body region and at least along said corner surface that abuts said body region, and wherein said trench is lined with a second insulative layer at least along said central bottom surface of said trench, said second insulative layer being coupled to said first insulative layer and said second insulative layer being thicker than said first insulative layer; and

a gate region coupled to said first insulative layer and said second insulative layer within said trench, so as to form an active corner region along at least a portion of said corner surface.

22. The trench-gated MOSFET of claim 21, further including a high conductivity region of said first conductivity type formed in said drain region adjacent to at least said central bottom surface of said trench.

23. The trench-gated MOSFET of claim 21, wherein said first insulative layer extends to the interface between said corner surface and said central bottom surface.

24. The trench-gated MOSFET of claim 23, wherein said body region extends to the interface between said corner surface and said central bottom surface.

25. The trench-gated MOSFET of claim 23, wherein said body region extends to a first distance along said corner surface of said trench.