CMOS transceiver having an integrated power amplifier

• US 6,850,117 B2
• Filed: 01/07/2003
• Issued: 02/01/2005
• Est. Priority Date: 09/15/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Atheros Communications Incorporated (Qualcomm, Inc.)
• Inventors: Yue, Patrick, Su, David, Weber, David J.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US10/338,585
• Publication Number:
  US 20030155976A1
• Time in Patent Office: 756 Days
• Field of Search: 330/277, 330/298, 330/307, 330/311
• US Class Current: 330/277
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03F 1/223 : with MOSFET's
• CPC Class Codes: H03F 2200/06 : A balun, i.e. balanced to or from unbalanced converter, being present at the input of an amplifier
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45652 : the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H04B 2001/0408 : with power amplifiers
• CPC Class Codes: Y10S 977/724 : Devices having flexible or movable element

Abstract

The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

Claims

1. An integrated circuit transistor structure for amplifying a radio frequency signal in a circuit having a reference DC voltage to obtain an amplified radio frequency signal to an output that has a load associated therewith comprising:

a first NMOS transistor having a first source connected to ground and a first gate for receiving the radio frequency signal, wherein the first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith;

a second NMOS transistor having a second source connected to a first drain of the first NMOS transistor, a second gate connected to the reference DC voltage, and a second drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the second drain of the second NMOS transistor, wherein the second gate is disposed above a second insulator, the second NMOS transistor having a second transconductance and a second breakdown voltage associated therewith;

other CMOS transceiver chip components on the integrated circuit; and

wherein the second insulator is thicker than the first insulator so that the first transconductance is greater than the second transconductance.

2. A transistor structure according to claim 1 wherein the second breakdown voltage is greater than the first breakdown voltage.

3. A transistor structure according to claim 1 wherein the second breakdown voltage is greater than the first breakdown voltage.

4. A transistor structure according to claim 1 wherein the second insulator is substantially the same thickness as the first insulator.

5. A transistor structure according to claim 1 wherein the integrated circuit transistor structure is disposed within a semiconductor chip package that contains a metal ground plane, and wherein each of the first and second NMOS transistors have a portion that is electrically connected to the ground plane.

6. A transistor structure according to claim 5 wherein the electrical connection to the ground plane includes an electrical connection through a bond pad.

7. A transistor structure according to claim 5 wherein the output for the amplified radio signal within 500 um of an edge of the integrated circuit.

8. A transistor structure according to claim 7 wherein the output for the amplified radio signal is connected to a terminal on a semiconductor chip package through a radio signal bond pad, the radio signal bond pad including less than all of a plurality of metal layers capable of being associated therewith.

9. A transistor structure according to claim 8 wherein the radio signal bond pad includes a diffusion layer in the substrate disposed therebelow.

10. A transistor structure according to claim 8 wherein the output for the amplified radio signal is not connected through the bottom two electrical layers on the radio signal bond pad that is capable of having five layers.

11. A transistor structure according to claim 1 further including an inductor disposed between the reference DC voltage and the output with the load associated therewith, wherein the reference DC voltage is Vdd and wherein the output with the load associated therewith can tolerate voltage amplitudes of approximately 2Vdd without exceeding the second breakdown voltage of the second NMOS transistor.

12. A transistor structure according to claim 11 wherein the inductor is a bondwire inductor.

13. A transistor structure according to claim 11 wherein the first and second NMOS transistors provide a last stage of a multi-stage amplifier, the multi-stage amplifier being disposed on the integrated circuit.

14. A transistor structure according to claim 1, further including a differential transistor structure formed of two circuits, each of the two circuits comprising the transistor structure recited in claim 1.

15. A transistor structure according to claim 1 wherein the first and second NMOS transistors provide a last stage of a multi-stage amplifier, the multi-stage amplifier being disposed on the integrated circuit.