Flat mount with at least one semiconductor chip

• US 6,850,420 B2
• Filed: 05/28/2002
• Issued: 02/01/2005
• Est. Priority Date: 11/25/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Reiner, Robert
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US10/156,508
• Publication Number:
  US 20020172016A1
• Time in Patent Office: 980 Days
• Field of Search: 361/734, 361/737, 361/738, 361/763, 361/766, 361/780, 361/782, 361/783, 361/793, 361/794, 361/811, 361/821, 257/679, 257/688, 235/488, 235/491, 235/492, 343/702, 343/872, 343/873, 340/572.7, 455/41.1
• US Class Current: 361/782
• CPC Class Codes: G07D 7/01 Testing electronic circuits therein
• CPC Class Codes: G07D 7/026 using capacitive sensors

Abstract

The flat mount assembly, or transponder, has at least one semiconductor chip that is connected to an antenna for interchanging data and power with an electronic apparatus. The antenna is formed of two electrical conductors. A conductive layer is formed on the mount in overlapping relationship with the electrical conductors of the antenna. The overlapping conductive layer results in greater capacitive coupling between the electronic apparatus and the flat mount assembly.

Claims

1. A flat mount assembly, comprising a flat mount, at least one semiconductor chip in or on said flat mount, an antenna formed of two electrical conductors connected to said at least one semiconductor chip for interchanging data and power with an electronic apparatus, and a conductive layer disposed on said mount and overlapping said electrical conductors of said antenna for improving a capacitive coupling between said antenna and the electronic apparatus.

2. The flat mount assembly according to claim 1, wherein each of said two electrical conductors overlaps with an associated said conductive layer.

3. The flat mount assembly according to claim 2, wherein a respective said conductive layer completely covers a respective said electrical conductor.

4. The flat mount assembly according to claim 1, which further comprises a dielectric, and wherein said conductive layer is located at a distance from said electrical conductors, separated by said dielectric.

6. The flat mount assembly according to claim 1, wherein said flat mount has a first main face and said electrical conductors are applied on said first main face.

7. The flat mount assembly according to claim 1, wherein said conductive layer is in direct electrical contact with said electrical conductors.

8. The flat mount assembly according to claim 1, wherein said conductive layer is arranged mirror-symmetrically with respect to said electrical conductors.

9. The flat mount assembly according to claim 1, wherein said electrical conductors are arranged symmetrically with respect to said semiconductor chip.

10. The flat mount assembly according to claim 1, wherein said semiconductor chip is disposed outside a mirror-image axis of said flat mount.

11. The flat mount assembly according to claim 1, wherein said flat mount is composed of paper.

12. The flat mount assembly according to claim 1, wherein a surface area of a respective said conductive layer is greater than a surface area of a respective said electrical conductor.

5. The flat mount assembly according to claim l, wherein said electrical conductors are embedded together with said semiconductor chip in said flat mount.