Wear leveling techniques for flash EEPROM systems
First Claim
1. A method of managing operation of an EEPROM mass storage system having at least one integrated circuit containing memory cells divided into a number of groups of memory cells that are erased together and which are then rewritten with data, comprising the steps of:
- monitoring a number of rewrite cycles directed at the groups of cells, determining when a predetermined imbalance exists in a number of rewrite cycles directed at the groups of cells, in response to such an imbalance, reassigning at least one of the groups of cells to receive data designated for at least another of the groups of cells in order to correct the imbalance during further rewrite cycles, and wherein data are subsequently rewritten in said at least another of the groups of cells.
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Abstract
A mass storage system made of flash electrically erasable and programmable read only memory (“EEPROM”) cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.
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Citations
12 Claims
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1. A method of managing operation of an EEPROM mass storage system having at least one integrated circuit containing memory cells divided into a number of groups of memory cells that are erased together and which are then rewritten with data, comprising the steps of:
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monitoring a number of rewrite cycles directed at the groups of cells, determining when a predetermined imbalance exists in a number of rewrite cycles directed at the groups of cells, in response to such an imbalance, reassigning at least one of the groups of cells to receive data designated for at least another of the groups of cells in order to correct the imbalance during further rewrite cycles, and wherein data are subsequently rewritten in said at least another of the groups of cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of managing operation of a rewritable non-volatile mass storage system divided into a number of groups of memory cells which are periodically rewritten with new data, wherein a target endurance limit of a maximum number of rewrite cycles is designated for the memory cells, comprising:
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monitoring a number of rewrite cycles directed at the groups of memory cells, determining, before any of the individual groups of memory cells reaches the target endurance limit of the maximum number of rewrite cycles, when a predetermined imbalance exists in a number of rewrite cycles experienced among the groups of memory cells, and in response to determining that such an imbalance exists, copying stored data from at least one of the groups of memory cells into at least another of the groups of memory cells, and reassigning said at least another of the groups of memory cells to receive data designated for said at least one of the groups of memory cells in order to correct the imbalance during further rewrite cycles. - View Dependent Claims (9, 10, 11, 12)
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Specification
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Current AssigneeSandisk Technologies Incorporated (Western Digital Corporation)
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Original AssigneeSanDisk Corporation (Western Digital Corporation), Western Digital Corporation
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InventorsGupta, Anil, Norman, Robert D., Lofgren, Karl M. J., Thelin, Gregory B.
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Primary Examiner(s)Nguyen, Viet Q.
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Application NumberUS10/428,422Publication NumberTime in Patent Office641 DaysField of Search365/185.29, 365/185.11, 365/185.33, 365/218US Class Current365/185.29CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 2212/1036 Life time enhancementG06F 2212/7211 Wear levelingG11C 16/349 Arrangements for evaluating...G11C 16/3495 Circuits or methods to dete...G11C 8/12 Group selection circuits, e...
