Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMS

• US 6,850,457 B2
• Filed: 01/10/2002
• Issued: 02/01/2005
• Est. Priority Date: 03/08/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Shore, Michael A., Mullarkey, Patrick J., Cowles, Timoty B.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/043,682
• Publication Number:
  US 20020126559A1
• Time in Patent Office: 1,118 Days
• Field of Search: 365/230.01, 365/230.04, 365/230.08, 711/202
• US Class Current: 365/230.08
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the half density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.

Claims

1. A circuit for remapping a specific row address bit to a specific column address bit, comprising:

a first latch coupled to receive the specific row address bit, the latch being operable to store the specific row address bit responsive to a row address store signal and to then output the stored row address bit;

a second latch coupled to receive a first set of column address bits and the specific column address bit, the latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and

a selector operable to select either the specific column address bit output from the first latch or the specific column address bit output from the second latch, the selected address bit being combined with the column address bits in the first set.

2. The remapping circuit of claim 1 wherein the selector comprises:

a first pass gate coupled between an output of the first latch and an address output terminal;

a second pass gate coupled between an output of the second latch and the address output terminal; and

a control circuit for enabling the first pass gate and disabling the second pass gate or disabling the first pass gate and enabling the second pass gate.

3. A dynamic random access memory (“

DRAM”

) comprising;

an array of memory cells arranged in rows and columns;

a circuit for remapping a specific row address bit to a specific column address bit, comprising;

a remapping latch coupled to receive the specific row address bit, the remapping latch being operable to store the specific row address bit responsive to a row address strobe signal and to then output the stored row address bit;

a column address latch coupled to receive a first set of column address bits and the specific column address bit, the column address latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and

a selector operable to select either the specific row address bit output from the remapping latch in a reduced density mode or the specific column address bit output from the column address latch in a full density mode, the selected address bit being combined with the column address bits in the first set to provide a composite column address;

a column decoder coupled to the selector to receive the composite column address and enable respective sense amplifiers corresponding thereto;

a row address latch structured to store a row address responsive to a row address strobe signal;

a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;

a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;

a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in the reduced density mode regardless of the state of the least significant bit of the row address; and

a data path coupled between the memory array and a data terminal.

4. The dynamic random access memory of claim 3 wherein the selector comprises:

a first pass gate coupled between an output of the column address latch and an address output terminal;

a second pass gate coupled between an output of the remapping latch and the address output terminal; and

a control circuit for enabling the first pass gate and disabling the second pass gate or disabling the first pass gate and enabling the second pass gate.

5. A computer system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a dynamic random access memory, comprising;

an array of memory cells arranged in rows and columns;

a circuit for remapping a specific row address bit to a specific column address bit, comprising;

a remapping latch coupled to receive the specific row address bit, the remapping latch being operable to store the specific row address bit responsive to a row address strobe signal and to then output the stored row address bit;

a column address latch coupled to receive a first set of column address bits and the specific column address bit, the column address latch being operable to store the first set of column address bits and the specific column address bit responsive to a column address strobe signal and to then output the stored column address bits, including the specific column address bit; and

a selector operable to select either the specific row address bit output from the remapping latch in a reduced density mode or the specific column address bit output from the column address latch in a full density mode, the selected address bit being combined with the column address bits in the first set to provide a composite column address;

a column decoder coupled to the selector to receive the composite column address and enable respective sense amplifiers corresponding thereto;

a row address latch structured to store a row address responsive to a row address strobe signal;

a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;

a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;

a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in the reduced density mode regardless of the state of the least significant bit of the row address; and

a data path coupled between the memory array and a data terminal.

6. The computer system of claim 5 wherein the selector comprises:

a first pass gate coupled between an output of the column address latch and an address output terminal;

a second pass gate coupled between an output of the remapping latch and the address output terminal; and

a control circuit for enabling the first pass gate and disabling the second pass gate or disabling the first pass gate and enabling the second pass gate.

7. A method of addressing a dynamic random access memory (“

DRAM”

) having a full density operating mode and a reduced density operating mode, the method comprising;

determining the operating mode of the DRAM;

storing a specific row address bit responsive to a row address strobe signal;

storing a first set of column address bits and a specific column address bit responsive to a column address strobe signal; and

in the full density operating mode, selecting the first set of column address bits and the specific column address bit that were stored responsive to the column address strobe signal;

in the reduced density operating mode, selecting the first set of column address bits that were stored responsive to the column address strobe signal and the specific row address bit that was stored responsive to the row address strobe signal; and

addressing a column of the DRAM using the selected address bits.

8. The method of claim 7, further comprising addressing a row of the DRAM, the method comprising:

storing a second set of row address bits along with the specific row address bit responsive to the row address strobe signal; and

addressing a row of the DRAM using the stored second set of row address bits.