Circuit and method for controlling a spread spectrum transition

• US 6,850,554 B1
• Filed: 11/09/1999
• Issued: 02/01/2005
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sha, I-Teh, Chen, Kuang-Yu, Chen, Albert
• Primary Examiner(s): Tse, Young T.
• Assistant Examiner(s): CHANG, EDITH M
• Application Number:
  US09/436,522
• Time in Patent Office: 1,911 Days
• Field of Search: 375/130, 375/149, 375/139, 375/140, 327/157, 327/148
• US Class Current: 375/140
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A circuit and method for controlling a spread spectrum transition are presented comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The second circuit may be configured to synchronize the command signal to a feedback signal. The sequence of spread spectrum ROM codes may be generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

Claims

1. A spread spectrum clock generator circuit comprising:

a first circuit configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal, wherein (i) said clock signal is spread spectrum modulated and (ii) said spread spectrum modulation of said clock signal is switched on in response to a first state of said command signal and switched off in response to a second state of said command signal; and

a second circuit configured to synchronize said command signal to a feedback signal, wherein said sequence of spread spectrum ROM codes is generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

2. The spread spectrum clock generator circuit according to claim 1, wherein said spread spectrum clock generator circuit is used with a motherboard or CPU.

3. The spread spectrum clock generator circuit according to claim 1, wherein said second circuit is further configured to generate one or more control signals in response to (i) said command signal and (ii) said feedback signal.

4. The spread spectrum clock generator circuit according to claim 3, wherein said second circuit comprises a first latch.

5. The spread spectrum clock generator circuit according to claim 4, wherein said second circuit further comprises a second latch.

6. The spread spectrum clock generator circuit according to claim 5, wherein said predetermined criteria further includes a predetermined maximum frequency for said clock signal.

7. The spread spectrum clock generator according to claim 3, wherein said first circuit further comprises:

a first multiplexer circuit configured to select one of said reference signal and a prescaled version of said reference signal in response to said one or more control signals; and

a second multiplexer circuit configured to select one of said clock signal and a prescaled version of said clock signal in response to said one or more control signals.

8. The spread spectrum clock generator circuit according to claim 1, wherein said predetermined criteria are applied to said clock signal during a transition period when the spread spectrum modulation is switching on or switching off.

9. The spread spectrum clock generator circuit according to claim 1, wherein said predetermined criteria includes a predetermined minimum frequency for said clock signal.

10. The spread spectrum clock generator circuit according to claim 1, wherein said predetermined mathematical formula is:

$\left[\begin{array}{c}\mathrm{X1}<br><br>\left(N+1\right)\\ \mathrm{X2}<br><br>\left(N+1\right)\\ \mathrm{X3}<br><br>\left(N+1\right)\end{array}\right]=\left[\begin{array}{ccc}0& -\frac{\mathrm{VCO}}{\mathrm{FBD}<br><br>\left(N+1\right)}& 0\\ \frac{\mathrm{CP}<br><br>\left(N+1\right)}{\mathrm{C1}}& -\frac{1}{\mathrm{C1}·<br><br>\mathrm{R1}}& -\frac{1}{\mathrm{C1}·<br><br>\mathrm{R1}}\\ 0& \frac{1}{\mathrm{C2}·<br><br>\mathrm{R1}}& -\frac{1}{\mathrm{C2}·<br><br>\mathrm{R1}}\end{array}\right]<br><br>\text{\hspace{1em}<br><br>}\left[\begin{array}{c}\mathrm{X1}<br><br>\left(N\right)\\ \mathrm{X2}<br><br>\left(N\right)\\ \mathrm{X3}<br><br>\left(N\right)\end{array}\right]*\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>t<br><br>\left(N\right)+\left[\begin{array}{c}{U}_1<br><br>\left(N+1\right)\\ U_2<br><br>\left(N+1\right)\\ U_3<br><br>\left(N+1\right)\end{array}\right]*\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>t<br><br>\left(N\right)+\left[\begin{array}{c}{X}_1<br><br>\left(N\right)\\ X_2<br><br>\left(N\right)\\ X_3<br><br>\left(N\right)\end{array}\right],$

where X represents a value of said clock signal, VCO represents a voltage controlled oscillator gain, C1 and C2 represent capacitance values, R1 represents a resistance value, FBD represents a feedback divider value, Δ

t (N) represents a time interval between a last time step and a present time, U represents said reference signal, CP represents a charge pump current and N represents a time step.

11. The spread spectrum clock generator circuit according to claim 1, wherein:

said sequence of spread spectrum ROM codes is optimized using a computer program to simulate transient behavior.

12. The spread spectrum clock generator according to claim 1, wherein a first frequency of said clock signal when said spread spectrum modulation is switched off is greater than a second frequency of said clock signal when said spread spectrum modulation is switched on.

13. A spread spectrum clock generator circuit comprising:

means for generating a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes and (iii) a command signal, wherein (i) said clock signal is spread spectrum modulated and (ii) said spread spectrum modulation of said clock signal is switched on in response to a first state of said command signal and switched off in response to a second state of said command signal; and

means for synchronizing said command signal to a feedback signal, wherein said sequence of spread spectrum ROM codes is generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

14. A method for controlling a spread spectrum transition comprising the steps of:

generating a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes and (iii) a command signal, wherein (i) said clock signal is spread spectrum modulated and (ii) said spread spectrum modulation of said clock signal is switched on in response to a first state of said command signal and switched off in response to a second state of said command signal; and

synchronizing said command signal to a feedback signal, wherein said sequence of spread spectrum ROM codes is generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

15. The method according to claim 14, wherein the step of generating said sequence of spread spectrum ROM codes further comprises the sub-steps of:

(A) selecting a number of ROM codes to be used to generate a spread spectrum modulation signal; and

(B) generating said number of ROM codes according to said predetermined mathematical formula.

16. The method according to claim 15, wherein the step of selecting said ROM codes further comprises the sub-steps of:

(A) initializing a phase lock loop (PLL) at power supply ramping;

(B) stabilizing said PLL with spread spectrum modulation switched off;

(C) loading said sequence of spread spectrum ROM codes;

(D) switching on spread spectrum modulation;

(E) recording a transient behavior of said clock signal until PLL is in spread spectrum steady-state;

(F) switching off spread spectrum modulation;

(G) recording the transient behavior of said clock signal until spread spectrum modulation is completely off;

(H) comparing recorded the transient behavior to predetermined criteria;

(I) if the recorded transient behavior does not meet said predetermined criteria, shifting said sequence of spread spectrum ROM codes, wherein a last ROM code is moved to a first position and remaining ROM codes are shifted one position forward;

(J) if the recorded transient behavior meets said predetermined criteria, finalizing said sequence of spread spectrum ROM codes; and

(K) repeating sub-steps (D) through (J) until said recorded transient response meets said predetermined criteria.

17. The method according to claim 16, wherein said sub-steps are performed by a computer program.

18. The method according to claim 14, wherein said step of generating said clock signal further comprises the sub-step of controlling a feedback divider with said sequence of spread spectrum ROM codes.

19. The method according to claim 14, wherein the step of synchronizing said command signal to said feedback signal further comprises generating one or more control signals in response to (i) said command signal and (ii) said feedback signal.

20. The method according to claim 19, wherein said one or more control signals are generated by one or more latches configured to sample said command signal in response to said feedback signal.

21. The method according to claim 19, further comprising the steps of:

selecting one of said reference signal and a prescaled version of said reference signal in response to said one or more control signals; and

selecting one of said clock signal and a prescaled version of said clock signal in response to said one or more control signals.

22. An apparatus comprising:

a first circuit configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, (iii) a command signal and (iv) a feedback signal; and

a second circuit configured to synchronize said command signal to said feedback signal, wherein said sequence of spread spectrum ROM codes is generated according to a predetermined mathematical formula a nd optimized using a computer program to simulate a transient behavior of said apparatus.

23. The apparatus according to claim 22, wherein said sequence of spread spectrum ROM codes is optimized in accordance with predetermined-criteria using said computer program to simulate the transient behavior of said apparatus in response to said command signal changing state.