Cache management instructions
First Claim
1. A method of managing a cache comprising:
- executing a cache management instruction that includes operands specifying one or more addresses within a main memory coupled to the cache, the operands comprising a starting address operand, a stride operand, and a count operand, wherein the cache management instruction is invoked by a software program, and managing data blocks within the cache based on the specified memory addresses.
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Accused Products
Abstract
The invention is directed to techniques for managing a cache within a processor using one or more machine instructions. The machine instructions may perform one or more operations on the cache. For example, victimize instructions, allocate instructions, and pre-fetch instructions can be executed in the processor as part of cache management. Moreover, these various cache management instructions may be defined by one or more operands that specify memory addresses within main memory, rather than addresses or identifiers that define locations within the cache. For this reason, a programmer may invoke these cache management instructions to direct the management of the cache without knowing the specific location of data within the cache.
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Citations
33 Claims
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1. A method of managing a cache comprising:
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executing a cache management instruction that includes operands specifying one or more addresses within a main memory coupled to the cache, the operands comprising a starting address operand, a stride operand, and a count operand, wherein the cache management instruction is invoked by a software program, and managing data blocks within the cache based on the specified memory addresses. - View Dependent Claims (2, 3, 4, 5)
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- 6. A method of compiling a software program comprising generating executable instructions including a cache management instruction having operands specifying one or more addresses within a main memory, the operands comprising a starting address operand, a stride operand and a count operand, wherein the cache management instruction directs management of data blocks within a cache coupled to the main memory based on the specified memory-addresses.
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10. A processor comprising:
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a cache having a plurality of data blocks; and
a functional unit adapted to execute a cache management instruction having operands specifying one or more addresses in a main memory coupled to the cache, the operands comprising a starting address operand, a stride operand, and a count operand, wherein the cache management instruction directs management of data blocks within the cache based on the specified memory addresses, wherein the cache management instruction is capable of being invoked by a software program. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A system including:
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a memory device;
a cache coupled to the memory device, the cache organized as a plurality of data blocks; and
a processor coupled to the cache, wherein the processor is adapted to execute a cache management instruction to manage the cache, the cache management instruction having operands that specify one or more addresses within the memory device, the operands comprising a starting address operand, astride operand, and a count operand, wherein the cache management instruction is capable of being invoked by a software program. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29)
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- 30. A computer readable medium having executable instructions for a programmable processor stored thereon, wherein the instructions include a cache management instruction that directs the programmable processor to manage data blocks within a cache based on one or more memory addresses in a main memory coupled to the cache, wherein the memory addresses are specified by operands of the cache management instruction, the operands comprising a starting address operand, a stride operand, and a count operand, wherein the cache management instruction is capable of being invoked by a software program.
Specification