Memory tester has memory sets configurable for use as error catch RAM, Tag RAM's, buffer memories and stimulus log RAM

• US 6,851,076 B1
• Filed: 09/28/2000
• Issued: 02/01/2005
• Est. Priority Date: 09/28/2000
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Singh, Preet P, Cook, John H III, Jordan, Stephen D
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US09/672,650
• Time in Patent Office: 1,587 Days
• Field of Search: 714718-719, 714/732, 714735-736, 365200-201
• US Class Current: 714/718
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

The various functions that are desirable for interior test memory within a memory tester are implemented in Memory Sets each serving as the host for one or sometimes more of such functions. For certain classes of testing a portion of interior test memory can be used as a Stimulus Log RAM that operates as an ideal DUT to create the correct conditions that are to exist in an actual DUT after testing. The actual part can then be tested, while the expected receive vectors are taken from the Stimulus Log RAM, and the comparison results sent to an ECR, Tag RAM'"'"'s, etc., as usual. In this way the test program does not have to create or contain within itself the particular receive vectors that are the expected response from the applied stimulus.

Claims

1. A method of testing a memory under test on a memory tester, the method comprising the steps of:

(a) applying the same sequence of transmit vectors to the memory under test and to a work memory within the memory tester, the sequence of transmit vectors causing the storing of test pattern data within the memories to which it is applied, the stored test pattern data in each memory being an end result remaining stored therein after the conclusion of the application of the entire sequence of transmit vectors; and

(b) subsequent to the conclusion of step (a), comparing the test pattern data content of the memory under test with the test pattern data content of the work memory.

2. A method as in claim 1 wherein the same sequence of transmit vectors is an instance of that sequence that is applied simultaneously to the memory under test and to the work memory.

3. A method as in claim 1 wherein the same sequence of transmit vectors is separate instances of that sequence that are applied at different times to the memory under test and to the work memory.

4. A method as in claim 1 wherein the work memory is a selectable portion of an interior test memory within the memory tester.

5. A method as in claim 4 further comprising the step of interleaving work memory transactions among banks of DRAM.

6. A method as in claim 4 further comprising the step of storing comparison results from step (b) in an error catch memory that is a portion of an interior test memory within the memory tester.

7. A method as in claim 6 further comprising the step of interleaving error catch memory transactions among banks of DRAM.

8. A method as in claim 4 wherein the interior test memory is comprised of a plurality of memory sets and the selectable portion is a segment of a memory set.

9. A method as in claim 8 further comprising the step of storing comparison results from step (b) in an error catch memory that is a portion of a memory set different than the memory set of which the work memory is a segment.