Semiconductor memory device having ECC type error recovery circuit

• US 6,851,081 B2
• Filed: 07/24/2001
• Issued: 02/01/2005
• Est. Priority Date: 07/27/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yamamoto, Kouji
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US09/910,915
• Publication Number:
  US 20020013924A1
• Time in Patent Office: 1,288 Days
• Field of Search: 714/6, 714/763, 714/752
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check

Abstract

A semiconductor memory device having an error check and correction (ECC) type error recovery circuit in which disposition of ECC cells is improved. The memory device comprises: a memory cell array including a plurality of normal cell array portions and an ECC cell array portion; an X decoder for selecting one of word lines in the memory cell array, the word lines extending from the X decoder to the memory cell array; an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, the cell data including data from normal cells and ECC cells of the selected word line. The ECC memory cell array portion is disposed at a location other than the far end of the word lines from the X decoder, that is, the ECC cell array portion is disposed at a location in which read out speed of data from ECC cell or cells does not become the worst speed in the memory device. Therefore, the worst data read out speed can be measured from outside.

Claims

1. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:

a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said BCC memory cell array portion including a plurality of ECO memory cells;

an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and

an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;

wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder.

2. A semiconductor memory device as set forth in claim 1, wherein said ECC memory cell array portion is disposed at the near end of said word lines on the side of said X decoder.

3. A semiconductor memory device as set forth in claim 1, wherein said at least one normal memory cell array portion comprises a plurality of normal memory cell array portions.

4. A semiconductor memory device as set forth in claim 1, further comprising a Y decoder and digit lines extending from said Y decoder toward said memory cell array.

5. A semiconductor memory device as set forth in claim 1, wherein said cell data is supplied to said ECC operation circuit via sense amplifiers.

6. A semiconductor memory device as set forth in claim 1, wherein said semiconductor memory device comprises a random access memory (RAM) device.

7. A semiconductor memory device as set forth in claim 1, wherein said semiconductor memory device comprises a read-only memory (ROM) device.

8. A semiconductor memory device as set forth in claim 1, wherein data read out from said normal memory cell array portions can be outputted to outside of said semiconductor memory device without undergoing ECC operation by said ECC operation circuit.

9. A semiconductor memory device as set forth in claim 1, wherein sad ECC memory cell array portion is disposed at a location other than the far end and a near end of said word lines from said X decoder.

10. A semiconductor memory device as set forth in claim 1, wherein sad ECC memory cell array portion is disposed at a location on said word lines between locations of at least two of the plurality of normal memory cells on said word lines.

11. A semiconductor memory device as set forth in claim 1, wherein a read out speed of data from said ECC memory cells in said ECC memory cell array portion is less than a read out speed of at least one of the plurality of normal memory cells in said normal memory cell array.

12. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:

a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said ECC memory cell array portion including a plurality of ECC memory cells;

an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and

an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;

wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder, and

wherein said ECC memory cell array portion is disposed at a middle portion of said memory cell array.

13. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:

a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said ECC memory cell array portion including a plurality of ECC memory cells;

an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and

an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;

wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder, and

wherein said ECC memory cell array portion is disposed substantially the central portion of said memory cell array.

14. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:

a memory cell array including a plurality of normal memory cell array portions and an ECC memory cell array portion, each of said normal memory cell array portions including a plurality of normal memory cells, and said ECC memory cell array portion including a plurality of ECC memory cells;

an X decoder for selecting one of word lines in said memory cell array, said word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array;

a Y decoder and digit lines extending from said Y decoder toward said memory cell array;

an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;

wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder.

15. A semiconductor memory device as set forth in claim 14, wherein said ECC memory cell array portion is disposed at a middle portion of said memory cell array.

16. A semiconductor memory device as set forth in claim 14, wherein said ECC memory cell array portion is disposed substantially at the central portion of said memory cell array.

17. A semiconductor memory device as set forth in claim 14, wherein said ECC memory cell array portion is disposed at a near end of said word lines on the side of said X decoder.

18. A semiconductor memory device as set forth in claim 14, wherein a selection time of said ECC memory cells in said ECC memory cell array portion is less than a selection time of at least one of the plurality of normal memory cells in said normal memory cell array.

19. A semiconductor memory device as set forth in claim 14, wherein said ECC memory cell array portion is disposed at a location on said word lines for limiting a time for selecting said ECC memory cells in said ECC memory cell array portion to a time that is less than a time for selecting at least one of the plurality of normal memory cells in said normal memory cell array.

20. A semiconductor memory device as set forth in claim 14, wherein said ECC memory cell array portion is disposed at a location on said word lines for limiting a read out speed of data from said ECC memory cells in said ECC memory cell array portion to a read out speed that is less than a read out speed of at least one of the plurality of normal memory cells in said normal memory cell array.