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Semiconductor memory device having ECC type error recovery circuit

  • US 6,851,081 B2
  • Filed: 07/24/2001
  • Issued: 02/01/2005
  • Est. Priority Date: 07/27/2000
  • Status: Active Grant
First Claim
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1. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:

  • a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said BCC memory cell array portion including a plurality of ECO memory cells;

    an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and

    an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;

    wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder.

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