Semiconductor memory device having ECC type error recovery circuit
First Claim
1. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:
- a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said BCC memory cell array portion including a plurality of ECO memory cells;
an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and
an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;
wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder.
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Abstract
A semiconductor memory device having an error check and correction (ECC) type error recovery circuit in which disposition of ECC cells is improved. The memory device comprises: a memory cell array including a plurality of normal cell array portions and an ECC cell array portion; an X decoder for selecting one of word lines in the memory cell array, the word lines extending from the X decoder to the memory cell array; an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, the cell data including data from normal cells and ECC cells of the selected word line. The ECC memory cell array portion is disposed at a location other than the far end of the word lines from the X decoder, that is, the ECC cell array portion is disposed at a location in which read out speed of data from ECC cell or cells does not become the worst speed in the memory device. Therefore, the worst data read out speed can be measured from outside.
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Citations
20 Claims
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1. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:
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a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said BCC memory cell array portion including a plurality of ECO memory cells;
an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and
an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;
wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:
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a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said ECC memory cell array portion including a plurality of ECC memory cells;
an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and
an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;
wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder, and wherein said ECC memory cell array portion is disposed at a middle portion of said memory cell array.
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13. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:
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a memory cell array including at least one normal memory cell array portion and an ECC memory cell array portion, said normal memory cell array portion including a plurality of normal memory cells, and said ECC memory cell array portion including a plurality of ECC memory cells;
an X decoder for selecting one of word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array; and
an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;
wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder, and wherein said ECC memory cell array portion is disposed substantially the central portion of said memory cell array.
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14. A semiconductor memory device having an error check and correction (ECC) type error recovery circuit comprising:
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a memory cell array including a plurality of normal memory cell array portions and an ECC memory cell array portion, each of said normal memory cell array portions including a plurality of normal memory cells, and said ECC memory cell array portion including a plurality of ECC memory cells;
an X decoder for selecting one of word lines in said memory cell array, said word lines in said memory cell array, said word lines extending from said X decoder to said memory cell array;
a Y decoder and digit lines extending from said Y decoder toward said memory cell array;
an ECC operation circuit for performing error check and correction based on cell data read out from a selected word line, said cell data including data from normal cells and ECC cells of said selected word line;
wherein said ECC memory cell array portion is disposed at a location other than the far end of said word lines from said X decoder. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification