MRAM sense layer area control

• US 6,852,550 B2
• Filed: 07/14/2003
• Issued: 02/08/2005
• Est. Priority Date: 08/29/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Drewes, Joel A., Tuttle, Mark E.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/617,719
• Publication Number:
  US 20040041184A1
• Time in Patent Office: 575 Days
• Field of Search: 360/324.2, 216/22, 216/40
• US Class Current: 438/3
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3268 the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
• CPC Class Codes: H01F 41/308 lift-off processes, e.g. ion milling, for trimming or patterning
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

This invention relates to MRAM technology and new MRAM memory element designs. Specifically, this invention relates to the use of ferromagnetic layers of different sizes in an MRAM element. This reduces magnetic coupling between a pinned layer and a sense layer and provides a more effective memory element. In addition, the design of the present invention reduces the instances of electrical shorts occurring between the ferromagnetic layers in an MRAM element

Claims

1. A method of fabricating a programmable resistance memory element, comprising the steps of:

forming a first ferromagnetic layer having at least one side wall;

forming a second ferromagnetic layer having at least one side wall; and

forming a barrier layer between said first ferromagnetic layer and said second ferromagnetic layer;

wherein said at least one side wall of said first ferromagnetic layer extends laterally beyond said at least one side wall of said second ferromagnetic layer and

wherein the relative magnetization directions of said first and said second ferromagnetic layers is programmable to set a resistance of said memory element.

2. A method of claim 1 wherein said at least one side wall of said first ferromagnetic layer extends laterally at least about 10 angstroms beyond said at least one side wall of said second ferromagnetic layer.

3. A method of claim 2 wherein said at least one side wall of said first ferromagnetic layer extends laterally about 200 angstroms beyond said at least one side wall of said second ferromagnetic layer.

4. A method of claim 1 wherein said first ferromagnetic layer has a thickness of about 20 angstroms to about 100 angstroms.

5. A method of claim 4 wherein said first ferromagnetic layer has a thickness of about 20 angstroms to about 50 angstroms.

6. A method of claim 1 wherein said second ferromagnetic layer has a thickness of about 20 angstroms to about 100 angstroms.

7. A method of claim 6 wherein said second ferromagnetic layer has a thickness of about 20 angstroms to about 50 angstroms.

8. A method of claim 1 further comprising the step of forming an antiferromagnetic layer over said second ferromagnetic layer.

9. A method of claim 8 wherein said antiferromagnetic layer has a thickness of about 70 angstroms to about 150 angstroms.

10. A method of claim 8 wherein said antiferromagnetic layer comprises iridium manganese.

11. A method of claim 8 further comprising the step of forming a protective layer over said antiferromagnetic layer.

12. A method of claim 11 further comprising the step of forming an etch mask on said protective layer.

13. A method of claim 12 further comprising the step of etching the formed layers back beyond said second ferromagnetic layer but before said first ferromagnetic layer, providing an etched memory element and a side wall for said second ferromagnetic layer.

14. A method of claim 13 wherein said step of etching ceases at said barrier layer.

15. A method of claim 13 further comprising the step of forming at least one spacer located over said first ferromagnetic layer and lateral to said second ferromagnetic layer.

16. A method of claim 15 wherein said at least one spacer comprises a dielectric material.

17. A method of claim 15 wherein said at least one spacer extends laterally at least about 10 angstroms beyond said side wall of said second ferromagnetic layer.

18. A method of claim 17 wherein said at least one spacer extends laterally about 200 angstroms beyond said side wall of said second ferromagnetic layer.

19. A method of claim 15 wherein said step of forming at least one spacer comprises the steps of:

forming a spacer-constituent layer on said etched memory element; and

etching said spacer-constituent element back forming an etched memory element having at least one spacer.

20. A method of claim 15 further comprising the step of etching said etched memory element having at least one spacer back beyond said first ferromagnetic layer.

21. A method of claim 1 further comprising the step of forming an antiferromagnetic layer beneath said first ferromagnetic layer.

22. A method of claim 21 wherein said antiferromagnetic layer has a thickness of about 70 angstroms to about 150 angstroms.

23. A method of claim 21 wherein said antiferromagnetic layer comprises iridium manganese.

24. A method of claim 21 further comprising the step of forming a protective layer over said antiferromagnetic layer.

25. A method of claim 24 further comprising the step of forming an etch mask on said protective layer.

26. A method of claim 25 further comprising the step of etching the formed layers back beyond said second ferromagnetic layer but before said first ferromagnetic layer, providing an etched memory element and side wall for said second ferromagnetic layer.

27. A method of claim 26 wherein the step of etching ceases at said barrier layer.

28. A method of claim 26 further comprising the step of forming at least one spacer located over said first ferromagnetic layer and lateral to said second ferromagnetic layer.

29. A method of claim 28 wherein said at least one spacer comprises a dielectric material.

30. A method of claim 28 wherein said at least one spacer extends laterally at least about 10 angstroms beyond said side wall of said second ferromagnetic layer.

31. A method of claim 30 wherein said at least one spacer extends laterally about 200 angstroms beyond said side wall of said second ferromagnetic layer.

32. A method of claim 28 wherein said step of forming at least one spacer comprises the steps of:

forming a spacer-constituent layer on said etched memory element; and

etching said spacer-constituent element back forming an etched memory element having at least one spacer.

33. A method of claim 28 further comprising the step of etching said etched memory element having at least one spacer back beyond said first ferromagnetic layer.

34. A method of fabricating a programmable resistance memory element comprising the steps of:

forming a first ferromagnetic layer having at least one side wall;

forming a barrier layer over said first ferromagnetic layer;

forming a second ferromagnetic layer over said barrier layer having at least one side wall; and

forming an antiferromagnetic layer for pinning one of said first and said second ferromagnetic layers;

wherein one of said first and said second ferromagnetic layers extends laterally at least about 10 angstroms beyond said at least one side wall of the other of said first and said second ferromagnetic layers; and

wherein the relative magnetization directions of said first and said second ferromagnetic layers is programmable to set a resistance of said memory element.

35. The method of claim 34, wherein said one of said first and said second ferromagnetic layers extends laterally from about 10 angstroms to about 200 angstroms beyond said at least one side wall of the other of said first and said second ferromagnetic layers.

36. The method of claim 35, wherein said one of said first and said second ferromagnetic layer extends laterally about 200 angstroms beyond said at least one side wall of the other of said first and said second ferromagnetic layers.

37. A method of fabricating a programmable resistance memory element comprising the steps of:

forming a substrate;

forming a seed layer comprising tantalum over said substrate;

forming a first ferromagnetic layer having at least one side wall formed over said seed layer;

forming a barrier layer comprising an aluminum oxide tunnel barrier formed over said first ferromagnetic layer;

forming a second ferromagnetic layer having at least one side wall formed over said barrier layer;

forming an antiferromagnetic layer comprising iridium manganese formed over said second ferromagnetic layer; and

forming a protective layer comprising tantalum formed over said antiferromagnetic layer;

wherein said at least one side wall of said first ferromagnetic layer extends laterally at least about 10 angstroms beyond said at least one side wall of said second ferromagnetic layer; and

wherein the relative magnetization directions of said first and said second ferromagnetic layers is programmable to set a resistance of said memory element.

38. A method of fabricating a programmable resistance memory element comprising the steps of:

forming a substrate;

forming a first seed layer comprising tantalum having at least one side wall formed over said substrate;

forming a second seed layer comprising nickel iron formed over said first seed layer;

forming an antiferromagnetic layer comprising iridium manganese formed over said second seed layer;

forming a first ferromagnetic layer having at least one side wall formed over said antiferromagnetic layer;

forming a barrier layer comprising an aluminum oxide tunnel barrier formed over said first ferromagnetic layer;

forming a second ferromagnetic layer having at least one side wall formed over said barrier layer; and

forming a protective layer comprising tantalum formed over said second ferromagnetic layer;

wherein said at least one side wall of said first ferromagnetic layer extends laterally at least about 10 angstroms beyond said at least one side wall of said second ferromagnetic layer; and

wherein the relative magnetization directions of said first and said second ferromagnetic layers is programmable to set a resistance of said memory element.