Semiconductor device fabrication method and semiconductor device fabrication apparatus

• US 6,852,553 B2
• Filed: 02/15/2001
• Issued: 02/08/2005
• Est. Priority Date: 02/15/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Takada, Susumu, Haga, Shigeru, Oba, Shiro, Koujiro, Iwamichi, Kakegawa, Yuji, Arai, Norinaga, Kobayashi, Yoshihiko, Ishizu, Akio, Ida, Tsutomu, Takashima, Kazutoshi
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Harrison, Monica D.
• Application Number:
  US10/129,305
• Publication Number:
  US 20030003622A1
• Time in Patent Office: 1,454 Days
• Field of Search: 438/14, 438/15, 438/16, 438/17, 438/18, 438/106, 361/679, 361/728, 361/736, 361/737, 361/738, 324/500, 295/921, 295/93
• US Class Current: 438/15
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16315 : Shape
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.

Claims

1. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto the wiring substrate; and

attaching a cap having a recognition mark on a surface thereof to the wiring substrate to cover the chip for a passive element and the chip for an active element.

2. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto the wiring substrate; and

inspecting a recognition mark of a cap having the recognition mark on a surface thereof and attaching the cap found to be non-defective in the inspection to the wiring substrate to cover the chip for a passive element and the chip for an active element.

3. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto each of plural wiring substrates formed on a matrix substrate; and

attaching a cap having a recognition mark on a surface thereof to each of the wiring substrates on the matrix substrate to cover the chip for a passive element and the chip for an active element on the wiring substrate.

4. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto the wiring substrate;

affixing a recognition mark to a surface of a cap; and

attaching the cap with the recognition mark thereon to the wiring substrate to cover the chip for a passive element and the chip for an active element,

the mounting of the chip for a passive element and the chip for an active element onto the wiring substrate, the affixing of the recognition mark to the cap, and the mounting of the cap, being performed as a series of continuous operations.

5. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto each of plural wiring substrates formed on a matrix substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto each of wiring substrates formed on the matrix substrate and found to be non-defective after inspection; and

attaching caps to only the non-defective wiring substrates to cover the chip for a passive element and the chip for an active element mounted on each of the wiring substrates.

6. A method of manufacturing a semiconductor device which is assembled by successively performing the steps of mounting a chip for a passive element, mounting a chip for an active element, both onto each of plural wiring substrates formed on a matrix substrate, reflow of solder, wire bonding, resin coating, affixing of a recognition mark to a cap, mounting of the cap to each of the wiring substrates, and substrate cutting, the method comprising the step of affixing a defect mark to a wiring substrate found to be defective in inspection out of the wiring substrates formed on the matrix substrate, the defect mark being recognized every time each of the passive element chip mounting step and subsequent steps is carried out and said steps being not performed for the wiring substrate with the defect mark put thereon.

7. A method of manufacturing a semiconductor device which is assembled by successively performing the steps of mounting a chip for a passive element, mounting a chip for an active element, both onto each of plural wiring substrates formed on a matrix substrate, reflow of solder, wire bonding, resin coating, affixing of a recognition mark to a cap, mounting of the cap to each of the wiring substrates, and substrate cutting, the method comprising the step of conducting inspection after each of said steps to recognize whether there is any defect in the inspected step, and affixing a defect mark to the wiring substrate concerned, the defect mark being recognized every time each of the passive element chip mounting step and subsequent steps is carried out and the steps which follow the inspected step found to include a defect being not performed.

8. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

printing solder to a terminal for the chip for a passive element;

thereafter applying solder by potting to a recess formed in the wiring substrate;

disposing the chip for a passive element onto the wiring substrate;

disposing the chip for an active element into the recess of the wiring substrate; and

performing the reflow of solder to mount the chip for a passive element and the chip for an active element on the wiring substrate by solder connection.

9. The method of claim 8, wherein when the solder is discharged from a nozzle for potting, the nozzle is moved at a shortest distance within the wiring substrate and also for another adjacent wiring substrate, allowing the solder to be discharged into the recess formed in each of the wiring substrates.

10. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

printing solder to a terminal for a passive element on the wiring substrate;

applying solder by potting to a recess formed in the wiring substrate;

disposing the chip for a passive element onto the wiring substrate;

disposing the chip for an active element into the recess formed in the wiring substrate; and

reflowing solder to mount the chip for a passive element and the chip for an active element on the wiring substrate by solder connection.

11. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing the chip for a passive element onto the wiring substrate;

thereafter, disposing the chip for an active element into a recess formed in the wiring substrate; and

mounting the chip for a passive element and the chip for an active element onto the wiring substrate by solder connection.

12. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

supplying and disposing the chip for a passive element stored in each of plural parts supply sections provided in a parts loading apparatus to the wiring substrate parts supply section by parts supply section, the parts loading apparatus being for loading the chip for a passive element onto the wiring substrate;

disposing the chip for an active element into a recess formed in the wiring substrate; and

mounting the chip for a passive element and the chip for an active element onto the wiring substrate by solder connection.

13. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

recognizing a printed solder pattern formed on a terminal for the chip for a passive element on the wiring substrate and disposing the chip for a passive element onto the printed solder pattern;

disposing the chip for an active element into a recess formed in the wiring substrate; and

mounting the chip for a passive element and the chip for an active element onto the wiring substrate by solder connection.

14. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing the chip for a passive element onto the wiring substrate;

supplying the chip for an active element stored in each of plural pellet supply sections provided in a pellet loading apparatus to the wiring substrate pellet supply section by pellet supply section, and disposing it into a recess formed in the wiring substrate, the pellet loading apparatus being for loading the chip for an active element onto the wiring substrate; and

mounting the chip for a passive element and the chip for an active element on the wiring substrate by solder connection.

15. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing the chip for a passive element onto the wiring substrate;

recognizing an edge portion of the recess formed in the wiring substrate and disposing the chip for an active element into the recess; and

mounting the chip for a passive element and the chip for an active element on the wiring substrate by solder connection.

16. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing the chip for a passive element onto each of plural wiring substrates formed on a matrix substrate, the wiring substrates being partitioned by dividing grooves;

disposing the chip for an active element into a recess formed in each of the wiring substrates;

mounting the chip for a passive element and the chip for an active element on each of the wiring substrates by solder connection; and

applying a sealing resin by potting to the recesses of the plural wiring substrates while avoiding the dividing grooves to seal the chips for an active element on the wiring substrates with the resin.

17. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto each of plural wiring substrates formed on a matrix substrate; and

inserting one of opposed hook support portions of each of caps into a corresponding one of hook holes obliquely which hook holes are formed in the matrix substrate, the hook support portions respectively supporting hooks which are engageable with each of the wiring substrates, to mount the caps to the matrix substrate,

thereby allowing the chip for a passive element and the chip for an active element on each of the wiring substrates of the matrix substrate to be covered with each of the caps.

18. The method of claim 17, wherein when mounting the plural caps to the matrix substrate, the hook support portion disposed on an adjacent cap-free side, out of the opposed hook support portions of each of the caps, is first inserted into the corresponding hook hole formed in the matrix substrate to mount each of the caps onto the matrix substrate.

19. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing and mounting the chip for a passive element and the chip for an active element onto each of plural wiring substrates formed on a matrix substrate;

inserting one of opposed hook support portions of each of caps into a corresponding one of hook holes obliquely which hook holes are formed in the matrix substrate, the hook support portions respectively supporting hooks which are engageable with each of the wiring substrates;

allowing a load to be applied by the associated wiring substrate to the one hook support portion inserted into the hook hole, thereby causing the one hook support portion to deflect within an elastic range thereof in a direction away from the other hook support portion, and disposing the hook of the other hook support portion at a position above an opposite hook hole formed in the matrix substrate;

inserting the other hook support portion into the opposite hook hole; and

releasing the load applied by the wiring substrate, allowing the hook of the one hook support portion and the hook of the other hook support portion to engage to the wiring substrate, and mounting the caps to the matrix substrate.

20. A method of manufacturing a semiconductor device which is assembled by mounting a chip for a passive element and a chip for an active element onto a wiring substrate, the method comprising the steps of:

disposing the chip for a passive element onto a selected wiring substrate as the wiring substrate;

disposing a selected chip for an active element as the chip for an active element into a recess formed in the wiring substrate; and

mounting the chip for a passive element and the chip fox an active element onto the wiring substrate by solder connection,

the selected wiring substrate and the selected chip for an active element being mounted in combination with each other so that characteristics of the semiconductor device fall under an allowable range.