Manufacturing method of semiconductor substrate

• US 6,852,604 B2
• Filed: 04/30/2003
• Issued: 02/08/2005
• Est. Priority Date: 05/23/2002
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Baba, Tomoya
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US10/425,619
• Publication Number:
  US 20030219954A1
• Time in Patent Office: 650 Days
• Field of Search: 438/373, 438/198
• US Class Current: 438/373
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76267 Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiGe layer in the substrate that become element isolation formation regions, and carrying out a heat treatment.

Claims

1. A manufacturing method of a semiconductor substrate comprising the steps of:

(a) forming a SiGe layer on a substrate of which the surface is made of silicon;

(b) further forming a semiconductor layer on the SiGe layer; and

(c) forming spaced apart trenches in the SiGe layer, and after the trenches have been formed implanting ions into bottoms of the trenches in the SiGe layer that become element isolation formation regions, and carrying out a heat treatment following said implanting.

2. The method according to claim 1, wherein the ions implanted in step (c) are selected from the group consisting of hydrogen, inert gases and elements of groups II to V and the dose of the ions is 1×

10¹⁵ cm<sup>−

2</sup>, or greater.

3. The method according to claim 1, wherein the ions implanted in step (c) are silicon ions, germanium ions or arsenic ions.

4. The method according to claim 1, wherein the ions are implanted into the bottoms of the trenches in step (c) but are not implanted into active regions of the SiGe layer which are to form source and/or drain regions of a transistor between the trenches.

5. The method according to claim 1, wherein the SiGe layer is formed so as to have a concentration of Ge of from 10 atom % to 50 atom % and so as to have a film thickness of from 50 nm to 500 nm.

6. The method according to claim 1, wherein the semiconductor layer is a SiGe layer with a concentration of Ge lower than the Ge concentration of the SiGe layer.

7. The method according to claim 1, wherein the semiconductor substrate is used for a MOS transistor.

8. A manufacturing method of a semiconductor substrate comprising:

(a) forming a layer comprising SiGe on a substrate of which the surface comprises silicon;

(b) further forming a semiconductor layer on the layer comprising SiGe;

(c) forming spaced apart trenches in the layer comprising SiGe and after forming the trenches implanting ions into bottoms of the trenches in the layer comprising SiGe which become element isolation formation regions and thereafter carrying out a heat treatment; and

(d) implanting ions into the substrate and carrying out a heat treatment, wherein step (d) is carried out after steps (a) and (b) and before step (c).

9. The method according to claim 8, wherein the ions implanted in step (c) are selected from the group consisting of hydrogen, inert gases and elements of groups II to V and the dose of the ions is 1×

10¹⁵ cm<sup>−

2</sup>, or greater.

10. The method according to claim 8, wherein the ions implanted in step (c) are silicon ions, germanium ions or arsenic ions.

11. The method according to claim 8, wherein the ions are implanted into the bottoms of the trenches in step (c) but are not implanted into active regions of the SiGe layer which are to form source and/or drain regions of a transistor between the trenches.

12. The method according to claim 8, wherein the ions implanted in step (d) are selected from the group consisting of hydrogen, inert gases and elements of group IV and the dose of the ions is 2×

10¹⁶ cm<sup>−

2</sup>, or less.

13. The method according to claim 12, wherein the ions are hydrogen ions, helium ions, neon ions, silicon ions, carbon ions or germanium ions.

14. The method according to claim 8, wherein the ion implantation of step (d) is carried out by adjusting the acceleration energy so that the implantation peak is located at a position in the silicon substrate in the vicinity of the SiGe/substrate interface.

15. The method according to claim 8, wherein the ion implantation of step (d) is carried out by adjusting the acceleration energy so that the implantation peak is located at a depth of 20 nm, or greater, in the substrate from the interface between the layer comprising SiGe and the substrate.

16. The method according to claim 8, wherein the amount of ions implanted in step (d) is smaller than the amount that allows SiGe to be completely relaxed.

17. The method according to claim 8, wherein the layer comprising SiGe is formed so as to have a concentration of Ge of from 10 atom % to 50 atom % and so as to have a film thickness of from 50 nm to 500 nm.

18. The method according to claim 8, wherein the semiconductor layer is a SiGe layer with a concentration of Ge lower than the Ge concentration of the layer comprising SiGe.

19. The method according to claim 8, wherein the semiconductor substrate is used for a MOS transistor.

20. A manufacturing method of a semiconductor substrate comprising:

(a) forming a layer comprising SiGe on a substrate comprising silicon;

(b) further forming a semiconductor layer on the layer comprising SiGe;

(c) implanting ions into regions of the layer comprising SiGe in the substrate which become element isolation formation regions and carrying out a heat treatment; and

(d′

) implanting ions that can create micro cavities into the substrate and carrying out a heat treatment, wherein step (d′

) is carried out after steps (a) and (b) and before step (c), and trenches of which the bottoms are located in the layer comprising SiGe are created in the regions that become the element isolation formation regions before the ion implantation of step (c) so that silicon ions are implanted in the bottoms of the trenches in step (c).

21. A method of making a semiconductor device including an isolation region, the method comprising:

providing a substrate;

forming a layer comprising SiGe so as to be supported by the substrate;

forming a semiconductor layer on the substrate over the layer comprising SiGe;

forming a trench in the layer comprising SiGe;

after forming the trench, implanting ions into a bottom portion of the trench in the layer comprising SiGe; and

at least partially filling the trench with an insulator to form the isolation region.

22. The method according to claim 21, wherein the ions are selected from the group consisting of hydrogen, inert gases and elements of groups II to V and the dose of the ions is 1×

10¹⁵ cm<sup>−

2</sup>, or greater.

23. The method according to claim 21, wherein the ions are silicon ions, germanium ions or arsenic ions.

24. The method according to claim 21, wherein the layer comprising SiGe is formed so as to have a concentration of Ge of from 10 atom % to 50 atom % and so as to have a film thickness of from 50 nm to 500 nm.

25. The method according to claim 21, providing first and second of the trenches, and forming a transistor on the substrate between first and second trenches.