Method of forming an inductor with continuous metal deposition
First Claim
1. A method of forming a monolithic inductor, the steps comprising:
- forming a first dielectric layer on a semiconductor substrate having device components;
forming first trenches in said first dielectric layer;
forming first barrier material liner on said first trench walls;
filling said first trenches with first metal and planarizing said first metal;
forming a second dielectric layer over said first dielectric film having filled first trenches;
forming first via-trench patterns in said second dielectric layer;
filling said first via-trench patterns with second barrier material and planarizing said second barrier material;
forming second trenches in said second dielectric layer between said second barrier material filled first via-trenches;
filling said second trenches with second metal and planarizing said second metal;
forming a third dielectric layer over said second dielectric film having second metal filled second trenches;
forming second via-trench patterns in said third dielectric layer;
filling said second via-trench patterns with third barrier material and planarizing said third barrier material;
forming third trenches in said second dielectric layer between said third barrier metal filled second via-trenches; and
filling said third trenches with third metal and planarizing said third metal.
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Accused Products
Abstract
A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.
17 Citations
17 Claims
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1. A method of forming a monolithic inductor, the steps comprising:
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forming a first dielectric layer on a semiconductor substrate having device components;
forming first trenches in said first dielectric layer;
forming first barrier material liner on said first trench walls;
filling said first trenches with first metal and planarizing said first metal;
forming a second dielectric layer over said first dielectric film having filled first trenches;
forming first via-trench patterns in said second dielectric layer;
filling said first via-trench patterns with second barrier material and planarizing said second barrier material;
forming second trenches in said second dielectric layer between said second barrier material filled first via-trenches;
filling said second trenches with second metal and planarizing said second metal;
forming a third dielectric layer over said second dielectric film having second metal filled second trenches;
forming second via-trench patterns in said third dielectric layer;
filling said second via-trench patterns with third barrier material and planarizing said third barrier material;
forming third trenches in said second dielectric layer between said third barrier metal filled second via-trenches; and
filling said third trenches with third metal and planarizing said third metal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification
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- Resources
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Current AssigneeChartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
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Original AssigneeChartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
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InventorsChu, Sanford, Chan, Lap, Ng, Chit Hwei, Verma, Purakh, Pradeep, Yelehanka Ramachandramurthy
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Primary Examiner(s)Zarabian, Amir
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Assistant Examiner(s)NOVACEK, CHRISTY L
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Application NumberUS10/427,287Publication NumberTime in Patent Office649 DaysField of Search438/381, 438/622, 438/623, 438/627, 438/637, 438/643US Class Current438/381CPC Class CodesH01F 17/0006 Printed inductances printed...H01L 23/5227 Inductive arrangements or e...H01L 28/10 InductorsH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
