Semiconductor device and method for producing the same

• US 6,852,616 B2
• Filed: 06/10/2002
• Issued: 02/08/2005
• Est. Priority Date: 11/29/2000
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Advanced Technologies Inc. (f/k/a Tessera Advanced Technologies, Inc.) (Adeia Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Watase, Kazumi, Kumakawa, Takahiro, Kainoh, Kazuyuki, Shimoishizaka, Nozomi, Sahara, Ryuichi
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Richards, N. Drew
• Application Number:
  US10/165,279
• Publication Number:
  US 20020151104A1
• Time in Patent Office: 974 Days
• Field of Search: 438/612, 438/613, 438/618, 438/623, 438/637, 438/640, 438/642, 438/643
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 : of an individual wire connector
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.

Claims

1. A method for producing a semiconductor device comprising:

a first step of forming on a semiconductor substrate on which at least one semiconductor element is provided a first element electrode and a second element electrode electrically connected to the semiconductor element;

a second step of forming an insulating film so as to cover the first element electrode and the second element electrode;

a third step of forming a first opening for exposing at least one portion of the first element electrode and a second opening for exposing at least one portion of the second element electrode by selectively removing the insulating film;

a fourth step of forming first substantially continuous, thin conductive film on the insulating film and within the first and second openings;

a fifth step of forming a second, thick conductive film selectively on the first, thin conductive film so as to fill up the first opening and the second opening and extend over portions of the first, thin conductive film between the first and second openings; and

a sixth step of patterning the first and second conductive films by removing only an upper portion of the selectively formed second, thick conductive film and portions of the first, thin conductive film uncovered by the second, thick conductive film, thereby forming a first external electrode connected to the first element electrode via the first opening immediately above the first element electrode, forming a second external electrode and forming a connecting wire having one end connected to the second element electrode via the second opening and the another end connected to the second external electrode on the insulating film.

2. The method for producing a semiconductor device of claim 1, wherein the semiconductor substrate is a semiconductor wafer;

and

the method further composes a step of dividing the semiconductor wafer into chips after the fourth step.

3. The method for producing a semiconductor device of claim 1, wherein the semiconductor substrate is obtained by dividing a semiconductor wafer into chips.

4. The method for producing a semiconductor device of claim 1, wherein the insulating film is made of elastic insulating material.

5. The method for producing a semiconductor device of claim 1, wherein the third step comprises a step of forming the first opening and the second opening so that each wall surface of the openings has an inclination of less than 90°

with respect to a surface of the semiconductor substrate.

6. The method for producing a semiconductor device of claim 1, wherein the third step comprises a step of forming the first opening and the second opening so that at least portions near the upper end and near the lower end of each wall surface of the openings have an inclination of less than 90°

with respect to a surface of the semiconductor substrate.

7. The method for producing a semiconductor device of claim 1, wherein

the first step comprises a step of forming a pair of third element electrodes electrically connected to the semiconductor element on the semiconductor substrate;

the third step comprises a step of forming a pair of third openings for exposing at least one portion of each of the pair of third element electrodes by selectively removing insulating film; and

the fourth, fifth and sixth steps forming a coil having ends, each of which is connected to a corresponding third element electrode via a corresponding third opening of the pair, on the insulating film.

8. The method for producing a semiconductor device of claim 1, further comprising a seventh step of forming a protective film having a property of repelling conductive material so as to cover the first external electrode, the second external electrode and the connecting wire and then selectively removing the protective film to form a fourth opening for exposing at least one portion of the first external electrode and a fifth opening for exposing at least one portion of the second external electrode, after the sixth step.

9. The method for producing a semiconductor device of claim 8, wherein the seventh step comprises a step of forming a first external electrode terminal connected to the first external electrode via the fourth opening immediately above the first external electrode and forming a second external electrode terminal connected to the second external electrode via the fifth opening immediately above the second external electrode.

10. The method for producing a semiconductor device of claim 1, wherein the first step comprises a step of forming a pair of third element electrodes electrically connected to the semiconductor element on the semiconductor substrate;

the method further comprising, between the first step and the second step, a step of forming a passivation film covering a surface of the semiconductor substrate except the first element electrode, the second element electrode and the pair of third element electrodes, then

forming a coil having ends, each of which is connected to a corresponding third element electrode of the pair, on the passivation film; and

the insulating film covers the passivation film and the coil.