Silicide-silicon oxide-semiconductor antifuse device and method of making

• US 6,853,049 B2
• Filed: 03/13/2002
• Issued: 02/08/2005
• Est. Priority Date: 03/13/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Herner, S. Brad
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US10/095,962
• Publication Number:
  US 20030173643A1
• Time in Patent Office: 1,063 Days
• Field of Search: 257529-530, 257/665
• US Class Current: 257/529
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.

Claims

1. An antifuse comprising:

a first silicide layer;

a grown silicon oxide antifuse layer on a first surface of the first silicide layer; and

a first semiconductor layer having a first surface in contact with the antifuse layer;

wherein an entire lower surface of the silicon oxide antifuse layer contacts the first silicide layer.

2. The antifuse of claim 1, wherein the first silicide layer is selected from a group consisting of cobalt, platinum, nickel, chromium and niobium silicide.

3. The antifuse of claim 2, wherein the first silicide layer comprises NiSi.

4. The antifuse of claim 2, wherein the first silicide layer comprises cobalt silicide.

5. The antifuse of claim 4, wherein:

the antifuse layer comprises a thermally grown silicon oxide layer;

the antifuse layer is capable of being selectively breached by passing a programming current between the first cobalt silicide layer and the first semiconductor layer; and

the first semiconductor layer comprises an intrinsic or lightly doped polysilicon or single crystalline silicon layer of a first conductivity type.

6. The antifuse of claim 5, further comprising a heavily doped second semiconductor layer of the first conductivity type having a first surface in contact with a second surface of the first semiconductor layer.

7. The antifuse of claim 6, wherein the first and second semiconductor layers comprise n-type polysilicon layers.

8. The antifuse of claim 7, further comprising a third semiconductor layer having a first surface in contact with a second surface of the first cobalt silicide layer.

9. The antifuse of claim 8, further comprising a second cobalt silicide layer having a first surface in contact with a second surface of the second semiconductor layer.

10. The antifuse of claim 9, wherein:

the third semiconductor layer is located above a substrate;

the first cobalt silicide layer is located on the third semiconductor layer;

the antifuse layer is located on the first cobalt silicide layer;

the first semiconductor layer is located on the antifuse layer;

the second semiconductor layer is located on the first semiconductor layer; and

the second cobalt silicide layer is located on the second semiconductor layer.

11. The antifuse of claim 10, wherein:

the antifuse layer is 2 to 15 nm thick;

the first and the second cobalt silicide layers are 30 to 100 nm thick;

the first semiconductor layer is 30 to 800 nm thick;

the second semiconductor layer is 30 to 500 nm thick; and

the third semiconductor layer is 30 to 500 nm thick.

12. The antifuse of claim 10, wherein:

the first cobalt silicide layer, the antifuse layer and the third semiconductor layer are located in one of a plurality of first spaced apart rail stacks;

the first semiconductor layer, the second semiconductor layer and the second cobalt silicide layer are located in one of a plurality of second spaced apart rail stacks;

planarized insulating fill is located between adjacent first and adjacent second rail stacks;

the first rail stacks are located below the second rail stacks; and

the first rail stacks extend perpendicular to the first rail stacks.

13. An antifuse array disposed above a substrate, comprising:

(a) a first plurality of first spaced apart rail stacks disposed at a first height in a first direction above the substrate,

wherein each first rail stack comprises;

a first cobalt silicide layer; and

a first thermally grown silicon oxide antifuse layer on the first cobalt silicide layer;

(b) a second plurality of second spaced apart rail stacks disposed at a second height above the first height and in a second direction different from the first direction,

wherein each second rail stack comprises;

a first intrinsic or lightly doped semiconductor layer of a first conductivity type in contact with the first antifuse layer; and

a second heavily doped semiconductor layer of the first conductivity type above the first semiconductor layer.

14. The array of claim 13, wherein:

the first and second semiconductor layers comprise polysilicon layers;

a first surface of the second semiconductor layer contacts a second surface of the first semiconductor layer; and

the first antifuse layer is capable of being selectively breached by passing a programming current between the first cobalt silicide layer and the first semiconductor layer.

15. The array of claim 13, wherein the first rail stacks further comprise a heavily doped third semiconductor layer having a first surface in contact with a second surface of the first cobalt silicide layer.

16. The array of claim 15, wherein the first, second and third semiconductor layers comprise n-type polysilicon layers.

17. The array of claim 15, wherein the first and second semiconductor layers comprise n-type polysilicon layers and the third semiconductor layer comprises a p-type polysilicon layer.

18. The array of claim 15, wherein the second rail stacks further comprise a second metal silicide layer having a first surface in contact with a second surface of the second semiconductor layer.

19. The array of claim 18, further comprising planarized insulating fill located between adjacent first rail stacks and adjacent second rail stacks.

20. The array of claim 18, further comprising:

(c) a second antifuse layer on the second cobalt silicide layer in the second rail stack.

21. The array of claim 20, further comprising:

(d) a third plurality of third spaced apart rail stacks disposed at a third height above the second height in the first direction,

wherein each third rail stack comprises;

a fourth intrinsic or lightly doped semiconductor layer of the first conductivity type in contact with the second antifuse layer;

a fifth heavily doped second semiconductor layer of the first conductivity type on the fourth semiconductor layer;

a third cobalt silicide layer on the fifth semiconductor layer; and

a third antifuse layer on the third cobalt silicide layer.

22. The array of claim 21, further comprising:

(e) a fourth plurality of fourth spaced apart rail stacks disposed at a fourth height above the third height in the second direction,

wherein each fourth rail stack comprises;

a sixth intrinsic or lightly doped semiconductor layer of the first conductivity type in contact with the third antifuse layer;

a seventh heavily doped second semiconductor layer of the first conductivity type on the sixth semiconductor layer;

a fourth cobalt silicide layer on the seventh semiconductor layer; and

a fourth antifuse layer on the fourth cobalt silicide layer.

23. The array of claim 15, wherein:

the first antifuse layer is 2 to 15 nm thick;

the first cobalt silicide layer is 30 to 100 nm thick;

the first semiconductor layer is 30 to 800 nm thick;

the second semiconductor layer is 30 to 500 nm thick; and

the third semiconductor layer is 30 to 500 nm thick.

24. The array of claim 13, wherein the first direction is perpendicular to the second direction.

25. A three dimensional antifuse array disposed above a substrate, comprising:

(a) the substrate;

(b) at least two sets of a plurality of first, laterally spaced apart rail stacks disposed substantially in a first direction, each set of first rail stacks is disposed at a different height above the substrate,

wherein each first rail stack comprises;

a first intrinsic or lightly doped semiconductor layer of a first conductivity type;

a second heavily doped semiconductor layer of the first conductivity type located over the first semiconductor layer;

a first metal or metal silicide layer located over the second semiconductor layer; and

a first antifuse layer located on the first metal or metal silicide layer; and

(c) at least one set of a plurality of second, laterally spaced apart rail stacks disposed substantially in a second direction different from the first direction, each set of the second rail stacks is disposed at a height between successive sets of first rail stacks,

wherein each second rail stack comprises;

a third intrinsic or lightly doped semiconductor layer of the first conductivity type located on the first antifuse layer;

a fourth heavily doped semiconductor layer of the first conductivity type located over the third semiconductor layer;

a second metal or metal silicide layer located over the fourth semiconductor layer; and

a second antifuse layer located on the second metal or metal silicide layer.

26. The array of claim 25, wherein the first semiconductor layer of at least one first rail stack is located on the second antifuse layer of at least one second rail stack.

27. The array of claim 26, wherein:

the first metal or metal silicide layer is a metal silicide selected from a group consisting of cobalt, platinum, nickel, chromium and niobium silicide; and

the second metal or metal silicide layer is a metal silicide selected from a group consisting of cobalt, platinum, nickel, chromium and niobium silicide.

28. The array of claim 27, wherein:

the first, second, third and fourth semiconductor layers comprise polysilicon layers;

the first metal or metal silicide layer comprises a cobalt silicide layer;

the second metal or metal silicide layer comprises a cobalt silicide layer;

the first antifuse layer comprises a thermally grown silicon oxide layer on the first cobalt silicide layer;

the first antifuse layer is capable of being selectively breached by passing a programming current between the first cobalt silicide layer and the third semiconductor layer; and

the second antifuse layer comprises a thermally grown silicon oxide layer on the second cobalt silicide layer.

29. The array of claim 28, wherein:

the second semiconductor layer is located on the first semiconductor layer;

the first metal or metal silicide layer is located on the second semiconductor layer; and

the fourth semiconductor layer is located on the third semiconductor layer; and

the second metal or metal silicide layer is located on the fourth semiconductor layer.

30. The array of claim 29, further comprising:

(d) a first partial rail stack disposed below a lower most first or second rail stack, the first partial rail stack comprising a third cobalt silicide layer and a third antifuse layer on the cobalt silicide layer; and

(e) a second partial rail stack disposed above an upper most first or second rail stack, the second partial rail stack comprising a fifth intrinsic or lightly doped semiconductor layer, a sixth heavily doped semiconductor layer of the first conductivity type located over the fifth semiconductor layer, and a fourth metal or metal silicide layer located over the sixth semiconductor layer.

31. The array of claim 30, comprising at least three sets of first rail stacks and at least two sets of second rail stacks.

32. The array of claim 28, wherein the first, second, third and fourth semiconductor layers comprise n-type polysilicon layers.

33. The array of claim 32, wherein:

the first and second antifuse layers are 2 to 15 nm thick;

the first and second metal silicide layers are 30 to 100 nm thick;

the first and third semiconductor layers are 30 to 800 nm thick; and

the second and fourth semiconductor layers are 30 to 500 nm thick.

34. The array of claim 25, wherein:

the first and the second rail stacks are disposed perpendicular to each other;

each of the first rail stacks consists of four layers; and

each of the second rail stacks consists of four layers.

35. The array of claim 25, wherein:

a first antifuse device is formed in the second semiconductor layer, the first metal or metal silicide layer and the first antifuse layer of one first rail stack and in the third semiconductor layer, the fourth semiconductor layer, and the second metal or metal silicide layer of an adjacent second rail stack overlying said first rail stack; and

a second antifuse device is formed in the fourth semiconductor layer, the second metal or metal silicide layer and the second antifuse layer of said second rail stack and in the first semiconductor layer, the second semiconductor layer, and the first metal or metal silicide layer of an adjacent first rail stack overlying said second rail stack.

36. The array of claim 25, further comprising planarized insulating fill located between adjacent first rail stacks and adjacent second rail stacks.

37. A method of making an antifuse comprising:

forming a first silicide layer over a substrate;

growing a silicon oxide antifuse layer on a first surface of the first silicide layer; and

forming a first semiconductor layer having a first surface in contact with the antifuse layer;

wherein an entire lower surface of the silicon oxide antifuse layer contacts the first silicide layer.

38. The method of claim 37, wherein the first silicide layer is selected from a group consisting of cobalt, platinum, nickel, chromium and niobium silicide.

39. The method of claim 38, wherein:

the first silicide layer comprises a first cobalt silicide layer;

growing the silicon oxide antifuse layer comprises thermally growing a silicon oxide layer; and

the first semiconductor layer comprises an intrinsic or lightly doped polysilicon or single crystalline silicon layer of a first conductivity type.

40. An antifuse comprising:

a first silicide layer;

a silicon oxide antifuse layer on a first surface of the first silicide layer;

a first semiconductor layer having a first surface in contact with the antifuse layer;

a second semiconductor layer having a first surface in contact with a second surface of the first semiconductor layer; and

a third semiconductor layer having a first surface in contact with a second surface of the first silicide layer.

41. The anti fuse of claim 40, wherein the first silicide layer is selected from a group consisting of cobalt, platinum, nickel, chromium and niobium silicide.

42. The antifuse of claim 41, wherein the first silicide layer comprises NiSi.

43. The antifuse of claim 41, wherein the first silicide layer comprises cobalt silicide.

44. The antifuse of claim 40, wherein:

the antifuse layer is capable of being selectively breached by passing a programming current between the first silicide layer and the first semiconductor layer; and

the first semiconductor layer comprises an intrinsic or lightly doped polysilicon or single crystalline silicon layer of a first conductivity type.

45. The antifuse of claim 44, wherein the second semiconductor layer comprises a heavily doped second semiconductor layer of the first conductivity type.

46. The antifuse of claim 45, wherein:

the antifuse layer comprises a thermally grown silicon oxide layer; and

the first and second semiconductor layers comprise n-type polysilicon layers.

47. The antifuse of claim 40, wherein an entire lower surface of the silicon oxide antifuse layer contacts the first silicide layer.