Semiconductor switching circuit device and manufacturing method thereof

• US 6,853,072 B2
• Filed: 04/16/2003
• Issued: 02/08/2005
• Est. Priority Date: 04/17/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Sakakibara, Mikito, Asano, Tetsuro
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/414,490
• Publication Number:
  US 20040021156A1
• Time in Patent Office: 664 Days
• Field of Search: 257/393, 257/183, 257/187, 333/262, 200/181
• US Class Current: 257/728
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48666 Titanium (Ti) as principal constituent
• CPC Class Codes: H01L 2224/48669 Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 29/4175 : for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Posts are disposed at the surroundings of an FET and a shield metal supported by the posts is placed above the FET to create a void between the FET and the shield metal. Since the separation between the FET and the shield metal is small, the resin does not enter the void. A resin layer cover the shield metal. The shield metal is connected to an electrode pad that receives a DC control signal. Although high frequency signals that are applied to the FET may leak between the source and drain electrodes of the FET through the resin layer covering the FET even when the FET is switched off, the void and the shield metal prevent such signal leakage.

Claims

1. A semiconductor switching circuit device comprising:

a field effect transistor comprising a source electrode, a gate electrode and a drain electrode;

a first electrode pad connected to the source electrode or the drain electrode;

a second electrode pad connected to the source electrode or the drain electrode which is not connected to the first electrode pad;

a metal layer disposed above the transistor so that a void is created between the metal layer and the transistor; and

a layer made of a resin disposed on the metal layer.

2. The semiconductor switching circuit device of claim 1, further comprising a post supporting the metal layer.

3. The semiconductor switching circuit device of claim 1, wherein the separation between the metal layer and the transistor is such that the resin does not enter the void when the layer made of the resin is formed on the metal layer.

4. The semiconductor switching circuit device of claim 3, wherein the separation is 0.5 μ

m to 3 μ

m.

5. The semiconductor switching circuit device of claim 1, wherein the metal layer comprises a layer formed by plating a metal.

6. The semiconductor switching circuit device of claim 1, wherein a plurality of openings are formed in the metal layer.

7. The semiconductor switching circuit device of claim 1, further comprising a third electrode pad receiving a DC voltage and applying the DC voltage to the field effect transistor, wherein the metal layer is connected to the third electrode pad.

8. The semiconductor switching circuit device of claim 1, wherein the metal layer covers the entire transistor.

9. The semiconductor switching circuit device of claim 1, wherein the void is filled with air.

10. The semiconductor switching circuit device of claim 1, wherein the post is in direct contact with a substrate on which the transistor if formed.

11. A semiconductor switching circuit device comprising:

a field effect transistor comprising a source electrode, a gate electrode and a drain electrode;

a signal input electrode pad receiving a high frequency signal and connected to the source electrode or the drain electrode;

a signal output electrode pad outputting the high frequency signal and connected to the source electrode or the drain electrode which is not connected to the signal input electrode pad;

a control electrode pad receiving a control signal and applying the control signal to the gate electrode; and

means for preventing the high frequency signal from leaking between the source electrode and the drain electrode when the field effect transistor is switched off and the high frequency signal is applied to the signal input electrode pad.

12. A semiconductor switching circuit device comprising:

a compound semiconductor substrate;

a field effect transistor formed on the substrate and comprising a source electrode, a gate electrode and a drain electrode;

a first electrode pad connected to the source electrode or the drain electrode;

a second electrode pad connected to the source electrode or the drain electrode which is not connected to the first electrode pad;

a metal post standing on a high impurity region formed on the substrate; and

a metal layer disposed above the transistor and supported by the metal post.

13. The semiconductor switching circuit device of claim 12, further comprising a third electrode pad receiving a DC voltage and applying the DC voltage to the transistor, wherein the metal layer is connected to the third electrode pad.

14. A semiconductor switching circuit device comprising:

a silicon substrate;

a field effect transistor formed on the substrate and comprising a source electrode, a gate electrode and a drain electrode;

a first electrode pad connected to the source electrode or the drain electrode;

a second electrode pad connected to the source electrode or the drain electrode which is not connected to the first electrode pad;

a metal post standing on a dielectric layer formed on the substrate; and

a metal layer disposed above the transistor and supported by the metal post.

15. The semiconductor switching circuit device of claim 14, wherein the dielectric layer is a LOCOS film.

16. The semiconductor switching circuit device of claim 14, further comprising a third electrode pad receiving a DC voltage and applying the DC voltage to the transistor, wherein the metal layer is connected to the third electrode pad.

17. A semiconductor switching circuit device comprising:

a silicon substrate;

a field effect transistor formed on the substrate and comprising a source electrode, a gate electrode and a drain electrode;

a first electrode pad connected to the source electrode or the drain electrode;

a second electrode pad connected to the source electrode or the drain electrode which is not connected to the first electrode pad;

a metal post standing on a portion of the substrate, the portion being at a ground voltage; and

a metal layer disposed above the transistor and supported by the metal post.