Method and probe card configuration for testing a plurality of integrated circuits in parallel
First Claim
1. A probe card configuration for testing a plurality of integrated circuits in parallel using a test system having electrical signal lines, the probe card configuration comprising:
- a carrier board for receiving said electrical signal lines of said test system, said carrier board defining a plane;
contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested, said contact-making needles for connection with said electrical signal lines of said test system to produce signal paths between said test system and the integrated circuits to be tested; and
a plurality of active modules configured on said carrier board, each one of said plurality of said active modules being assigned to one of the integrated circuits to be tested in parallel, each one of said plurality of said active modules being inserted into ones of the signal paths that are between said test system and the respective assigned one of the integrated circuits to be tested, each one of said plurality of said active modules having a longest extent;
said longest extent of each one of said plurality of said active modules being configured non-parallel with said plane of said carrier board.
9 Assignments
0 Petitions
Accused Products
Abstract
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.
-
Citations
6 Claims
-
1. A probe card configuration for testing a plurality of integrated circuits in parallel using a test system having electrical signal lines, the probe card configuration comprising:
-
a carrier board for receiving said electrical signal lines of said test system, said carrier board defining a plane;
contact-making needles for producing electrical connections with contact areas on the integrated circuits to be tested, said contact-making needles for connection with said electrical signal lines of said test system to produce signal paths between said test system and the integrated circuits to be tested; and
a plurality of active modules configured on said carrier board, each one of said plurality of said active modules being assigned to one of the integrated circuits to be tested in parallel, each one of said plurality of said active modules being inserted into ones of the signal paths that are between said test system and the respective assigned one of the integrated circuits to be tested, each one of said plurality of said active modules having a longest extent;
said longest extent of each one of said plurality of said active modules being configured non-parallel with said plane of said carrier board. - View Dependent Claims (2, 3, 4, 5, 6)
-
Specification