Method and system having switching network for testing semiconductor components on a substrate

• US 6,853,211 B2
• Filed: 08/01/2003
• Issued: 02/08/2005
• Est. Priority Date: 05/11/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: de Varona, Jorge L., Akram, Salman, Doherty, C. Patrick
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US10/633,189
• Publication Number:
  US 20040021480A1
• Time in Patent Office: 557 Days
• Field of Search: 324/765, 324/158.1, 324/754, 324/755, 324/758, 438/14, 438/17, 438/18, 438/16, 257/48
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A system for testing semiconductor components contained on a substrate, such as a wafer, a panel, a leadframe or a module, includes an interconnect configured to electrically engage all of the components on the substrate at the same time. The interconnect includes a switching network configured to selectively apply test signals to selected components, to electrically isolate defective components and to transmit test signals from selected groups of components. The system also includes a test apparatus, such as a wafer prober or a carrier for handling the substrate. A method for testing includes the steps of providing the interconnect having the switching network, and controlling test signals to the components using the switching network to perform various test procedures, such as functionality tests, parametric tests and burn-in tests.

Claims

1. A system for testing semiconductor components on a substrate comprising:

an interconnect comprising a plurality of interconnect contacts configured to electrically engage the components;

a switching network in electrical communication with the interconnect contacts;

a tester configured to transmit test signals through the switching network and the interconnect to the components;

the switching network configured to multiply and selectively transmit the test signals, to electrically isolate non-functional components and to read test signals from selected groups of components.

2. The system of claim 1 further comprising a carrier containing the interconnect configured to hold the substrate.

3. The system of claim 2 wherein the carrier is configured for placement in a burn-in oven.

4. The system of claim 3 further comprising a wafer prober containing the interconnect configured to handle the substrate.

5. The system of claim 1 wherein the switching network comprises a die on the interconnect.

6. The system of claim 1 wherein the interconnect comprises a semiconductor material and the switching network comprises active electrical devices in the material.

7. The system of claim 1 wherein the components comprise dice and the substrate comprises a wafer.

8. The system of claim 1 wherein the components comprise packages and the substrate comprises a leadframe or a panel.

9. A system for testing semiconductor components on a substrate comprising:

a testing apparatus comprising an interconnect configured to electrically engage the components on the substrate;

a tester in electrical communication with the interconnect configured to generate and analyze test signals for testing the components; and

a switching network on the testing apparatus in electrical communication with the interconnect configured to control test signals applied through the interconnect to the components.

10. The system of claim 9 wherein the testing apparatus comprises a wafer prober.

11. The system of claim 9 wherein the testing apparatus comprises a carrier configured to hold the substrate.

12. The system of claim 9 wherein the testing apparatus comprises a tester and the switching network is configured to expand resources of the tester by transmitting read test signals from selected groups of components.

13. The system of claim 9 wherein the switching network comprises a plurality of active electrical switching devices.

14. The system of claim 9 wherein the substrate comprises a wafer and the components comprise dice on the wafer.

15. The system of claim 9 wherein the substrate compress a leadframe and the components comprise packages on the leadframe.

16. The system of claim 9 wherein the substrate comprises a panel and the components comprise packages on the panel.

17. A system for testing semiconductor components on a substrate comprising:

a carrier configured to hold the substrate;

an interconnect on the carrier configured to electrically engage the components held by the carrier; and

a switching network on the carrier configured to selectively control applying of test signals through the interconnect to the components.

18. The system of claim 17 wherein the substrate comprises a wafer, a panel, a leadframe or a module.

19. The system of claim 17 wherein the carrier comprises a base for mounting the interconnect, a cover for holding the substrate, and a force applying mechanism for biasing the substrate and the interconnect together.

20. The system of claim 17 wherein the carrier comprises an alignment member configured to align the substrate on the carrier.

21. The system of claim 17 wherein the substrate comprises a wafer and the components comprise semiconductor dice.

22. The system of claim 17 wherein the substrate comprises a panel and the components comprise semiconductor packages.

23. The system of claim 17 wherein the substrate comprises a leadframe and the components comprise semiconductor packages.

24. The system of claim 17 wherein the carrier is configured for placement in a burn-in oven and the test signals include burn in test signals.

25. A method for testing semiconductor components on a substrate comprising:

providing a carrier configured to hold the substrate;

providing a switching network on the carrier;

applying test signals through the switching network to the components; and

controlling the test signals using the switching network to perform a selected test on the components.

26. The method of claim 25 wherein the carrier includes an interconnect for electrically engaging the components and the switching network is contained on the interconnect.

27. The method of claim 25 wherein the test signals are configured to perform functionality testing of the components.

28. The method of claim 25 wherein the test signals are configured to perform burn-in testing of the components.

29. The method of claim 25 wherein the test signals are configured to perform functionality testing and burn-in testing of the components.

30. The method of claim 25 wherein the substrate comprises a wafer, a panel, a leadframe or a module.

31. The method of claim 25 wherein the switching network comprises a die on the carrier.

32. A method for testing semiconductor components on a substrate comprising:

providing a switching network;

applying burn-in test sign is through the switching network to the components on the substrate; and

electrically isolating at east one component on the substrate during the applying step using the switching network.

33. The method of claim 32 wherein the applying step is performed using a carrier.

34. The method of claim 33 wherein the substrate comprises a panel and the carrier configured to hold the panel in a burn-in oven.

35. The method of claim 33 wherein the substrate comprises a leadframe and the carrier is configured to hold the leadframe in a burn-in oven.

36. The method of claim 33 wherein the switching network is contained on an interconnect in the carrier configured to electrically engage the components.

37. The method of claim 36 wherein the switching network comprises a die or active electrical switching devices on the interconnect.

38. The method of claim 32 further comprising applying parametric test signals through the switching network prior to he electrically isolating step.

39. A method for testing semiconductor components on a substrate comprising:

providing a switching network;

applying test signals through the switching network to the components on the substrate; and

controlling the test signals using the switching network to perform a selected test on each component on the substrate.

40. The method of claim 39 wherein the selected test comprises functionality testing.

41. The method of claim 39 wherein the selected test comprises parametric testing.

42. The method of claim 39 wherein the selected test comprises burn-in testing.

43. The method of claim 39 wherein the substrate comprises a wafer and the components comprise semiconductor dice.

44. The method of claim 39 wherein the substrate comprises a panel and the components comprise semiconductor packages.

45. The method of claim 39 wherein the substrate comprises a leadframe and the components comprise semiconductor packages.