Display device

• US 6,853,371 B2
• Filed: 09/17/2001
• Issued: 02/08/2005
• Est. Priority Date: 09/18/2000
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Senda, Michiru, Miyajima, Yasushi
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): PRIZIO JR, PETER
• Application Number:
  US09/953,237
• Publication Number:
  US 20020036612A1
• Time in Patent Office: 1,240 Days
• Field of Search: 345/90, 345/92, 345/205, 345/206, 345/204, 345/55, 345/87, 345/98
• US Class Current: 345/206
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

Within one pixel element 200, two display circuits corresponding to the analog display mode and the digital display mode are disposed such that they are adjacent to each other. One of these two display circuits can be selected through the circuit selection circuits 40 or 43. Since the high voltage power line 150 of the retaining circuit 110, which is used under the digital display mode, also performs as the signal selection line 88, it is possible to have the high density integration of the pixel element 200. Also, the bias voltage Vsc supplied through the selection storage capacitor line 81 is same as the signal A. Therefore, the storage capacitor line 81 is connected to the drain of the TFT 122 of the signal selection circuit 120 so that the signal line 82 for supplying the signal A can be omitted. Thus, the high-density integration of the pixel element 200 can be achieved.

Claims

1. A display device comprising:

a plurality of gate signal lines disposed in a predetermined direction on a substrate;

a plurality of drain signal lines disposed in a direction different from the predetermined direction;

a plurality of pixel elements which are disposed as a matrix, activated by a scanning signal fed through the gate signal line and provided with an image signal fed through the drain signal line;

a pixel electrode provided within the pixel elements;

a first display circuit which is disposed for the pixel elements and provides the pixel elements with the image signals;

a second display circuit which is disposed for the pixel elements, include a retaining circuit holding the image signal and provides the pixel electrode with an voltage corresponding to the image signal retained by the retaining circuit; and

a circuit selection circuit for selecting one of the first and second display circuit in response to a circuit selection signal disposed for the pixel elements;

wherein the circuit selection signal is supplied to the circuit selection circuit through an electric power line which is used for supplying a power voltage to the retaining circuit.

2. The display device of claim 1, wherein the retaining circuit comprises two inverter circuits which are positively fed back to each other, said inverter circuits being provided with a high voltage power line and a low voltage power line, said high voltage power line being used for supplying the circuit selection signal to the circuit selection circuit.

3. The display device of claim 2, wherein the circuit selection circuit comprises a first switching element for selecting the first display circuit and a second switching circuit for selecting the second display circuit, said first and second switching elements complimentarily performing a switching operation in response to the circuit selection signal supplied through the high voltage power line.

4. The display device of claim 3, wherein the first switching element comprises a thin film transistor of a first channel type, and the second switching element comprises a thin film transistor of a second channel type.

5. The display device of claim 1, wherein the retaining circuit comprises two inverter circuits which are positively fed back to each other, said inverter circuits being provided with a high voltage power line and a low voltage power line, said low voltage power line being used for supplying the power voltage to the retaining circuit.

6. The display device of claim 5, wherein the circuit selection circuit comprises a first switching element for selecting the first display circuit and a second switching circuit for selecting the second display circuit, said first and second switching elements complimentarily performing a switching operation in response to the circuit selection signal supplied through the low voltage power line.

7. The display device of claim 6, wherein the first switching element comprises a thin film transistor of a first channel type, and the second switching element comprises a thin film transistor of a second channel type.

8. A display device, comprising:

a plurality of gate signal lines disposed in a predetermined direction on a substrate;

a plurality of drain signal lines disposed in a direction different from the predetermined direction;

a plurality of pixel elements which are disposed as a matrix, activated by a scanning signal fed through the gate signal line and provided with an image signal fed through the drain signal line;

a first display circuit which has a storage capacitor element for holding an analog image signal fed through the drain signal line in response to a signal fed through the gate signal line and supplies the signal held by the storage capacitor element to a pixel electrode;

a second display circuit which is disposed near the first display circuit, includes a retaining circuit holding a digital image signal fed through the drain signal line in response to the signal fed through the gate signal line and a signal selection circuit for selecting one of the signals fed through a first and second signal lines for supplying said one of the signals to the pixel electrode; and

,

a circuit selection circuit for selecting one of the first and second display circuit in response to a circuit selection signal;

wherein one of the first and second signal lines works as a storage capacitor line for biasing an electrode of the storage capacitor element.

9. The display device of claim 8, wherein the signal supplied to the storage capacitor line is the same as the signal supplied to a common electrode working in accordance with the pixel electrode.