Non-volatile memory with test rows for disturb detection

• US 6,853,598 B2
• Filed: 02/14/2003
• Issued: 02/08/2005
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/367,014
• Publication Number:
  US 20030161205A1
• Time in Patent Office: 725 Days
• Field of Search: 365/201, 365/196
• US Class Current: 365/201
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.

Claims

1. A non-volatile memory device comprising:

an array of reprogrammable non-volatile memory cells arranged in rows and columns;

a plurality of bit lines coupled to the non-volatile memory cells;

a driver circuit coupled to the plurality of bit lines; and

test rows coupled to the array.

2. The non-volatile memory device of claim 1 wherein the non-volatile memory cells are floating gate transistors.

3. The non-volatile memory device of claim 1 wherein the test rows comprise two rows.

4. The non-volatile memory device of claim 1 wherein the driver circuit comprises first and second bit line drivers, and the test rows comprise first and second pairs of test rows respectively located adjacent to the first and second bit line drivers.

5. The non-volatile memory device of claim 1 wherein the test rows are located near the driver circuit.

6. A non-volatile memory device comprising:

an array of reprogrammable non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells;

X distributed driver circuits coupled to the bit line; and

X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits.

7. The non-volatile memory device of claim 6 wherein X equals two and the two pairs of addressable test rows are each located at an end of the bit line.

8. A non-volatile memory device comprising:

an array of reprogrammable non-volatile memory cells arranged in rows and columns;

a bit line having a resistance of R and coupled to the non-volatile memory cells;

X distributed driver circuits coupled to the bit line;

X pairs of addressable test rows coupled to the array and respectively located near the X driver circuits; and

wherein reprogammable non-volatile memory cell are floating gate transistors.

9. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines; and

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits.

15. The memory device of claim 9 wherein the first and second sets of test rows are patterned in a manner similarly to the rows of the array of memory cells.

10. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein the first and second driver circuits are located at an end of the plurality of bit lines.

16. The memory device of claim 10 further comprising:

a third driver circuit electrically coupleable to the plurality of bit lines, wherein the third driver circuit is not located near an end of the plurality of bitlines; and

a third set of test rows coupled to the array and respectively located near the third driver circuit.

11. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein the memory device is adapted to activate the first and second driver circuits simultaneously to drive data on the plurality of bit lines.

12. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein the memory device is adapted to activate the first and second driver circuits independently to drive data on the plurality of bit lines.

13. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein the memory device is adapted to activate the first and second driver circuits independently to drive data on the plurality of bit lines and wherein the memory device is adapted to place an un-activated driver circuit in a tri-state condition.

14. A memory device comprising:

an array of reprogrammable memory cells arrange in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

a first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

a disturb circuit coupled to the first and second sets of test rows, wherein the disturb circuit is adapted to determine if the memory cells of the first and second sets of addressable memory cell test rows have been disturbed.

17. A memory device comprising:

an array of reprogrammable memory cells arranged in rows and columns;

a plurality of bit lines coupled to the memory cells;

a first and second driver circuits electrically coupleable to the plurality of bit lines;

first and second sets of test rows coupled to the array and respectively located near the first and second driver circuits; and

wherein reprogrammable memory cells are floating gale transistors.