Efficient interpolator for high speed timing recovery

• US 6,854,002 B2
• Filed: 05/16/2003
• Issued: 02/08/2005
• Est. Priority Date: 12/24/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics NV
• Original Assignee: STMicroelectronics NV
• Inventors: Conway, Thomas, Byrne, Jason
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US10/439,401
• Publication Number:
  US 20030182335A1
• Time in Patent Office: 634 Days
• Field of Search: 708/313, 708/316, 708/319
• US Class Current: 708/313
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10055 using partial response filtering when writing the signal to the medium or reading it therefrom
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: G11B 20/10296 using the Viterbi algorithm
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels

Abstract

A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Claims

1. A circuit comprising:

a plurality of n multipliers, each multiplier having a first input and a second input, n being an integer greater than one;

a coefficient memory having at least n outputs, each output of the coefficient memory being coupled to a respective one of the multipliers at the first multiplier input;

a select circuit comprising a plurality of n multiplexers and having at least n output nodes, each of the n output nodes being coupled to a respective one of the multipliers at the second multiplier input, wherein each multiplexer includes first and second inputs and wherein each of the multiplexers are labeled as a first multiplexer, a second multiplexer and so on to an nth multiplexer; and

a plurality of input nodes coupled to the select circuit such that at a first time each of the input nodes is coupled to a respective one of the output nodes of the select circuit and such that at a second time at least some of the input nodes are coupled to a different one of the output nodes of the select circuit, wherein the input nodes are labeled as a first node, a second node and so on to an nth node, and wherein each input node is coupled to a corresponding first input of a respective one of the multiplexers such that the input nodes are coupled to the first input of the multiplexer in an forward order wherein the first input node is coupled to the first input of the first multiplexer, the second input node is coupled to the first input of the second multiplexer and the nth input node is coupled to the first input of the nth multiplexer and wherein each input node is also coupled to a corresponding second input of a respective one of the multiplexers such that the input modes are coupled to the second input of the multiplexers in a backward order wherein the first input node is coupled to the second input of the nth multiplexer, the second input node is coupled to the second input of the (n−

1)th multiplexer and the nth input node is coupled to the second input of the first multiplexer.

2. The circuit of claim 1 wherein each of the multipliers further includes an output, each of the multiplier outputs being coupled to a summer.

3. The circuit of claim 1 wherein the coefficient memory comprises a ROM.

4. The circuit of claim 1 wherein the input nodes are coupled to a sequence of data pulses.

5. The circuit of claim 4 wherein the sequence of data pulses are provided by a second select circuit.

6. A data processing circuit comprising:

a digital data source having an output carrying a sequence of digital signals having a period;

pre-filter with an input coupled to the output of the digital data source, wherein a sequence of digital signals carried at the first output of the pre-filter is time-shifted relative to a sequence of digital signals carried at the second output of the pre-filter, the time-shift equal to about one half of the period of the sequence of digital signals,

an interpolation circuit with a first input coupled to a first output of the pre-filter and a second input coupled to a second output of the pre-filter, wherein the interpolation circuit includes;

a plurality on n multipliers, each multiplier having a first input and a second input, n being an integer greater than one; and

a select circuit having at least n output nodes, each of the at least n output nodes being coupled to a respective one of the plurality of n multipliers at the first input, the select circuit having at least n input nodes,

wherein the select circuit couples the at least n input nodes to the at least n output nodes in a first order if a magnitude of a time shift is less than a first fraction of the period and couples the at least n input nodes to the at least n output nodes in a second order if the magnitude of the time shift is greater than the first fraction of the period.

7. The circuit of claim 6 wherein the interpolation circuit further includes a first plurality of serially coupled delay circuits and a second plurality of serially coupled delay circuits, the first pre-filter output being coupled to a first delay circuit in the first plurality of serially coupled delay circuits and the second pre-filter output being coupled to a first delay circuit in the second plurality of serially coupled delay circuits.

8. The circuit of claim 7 wherein the interpolation circuit further includes a plurality of multiplexers, each multiplexer including a first input coupled to one of the delay circuits in the first plurality of delay circuits, each multiplexer also including a second input coupled to one of the delay circuits in the second plurality of delay circuits, each multiplexer also including an output.

9. The circuit of claim 6 wherein the interpolation circuit further comprises a coefficient memory having at least n outputs, each output of the coefficient memory being coupled to a respective one of the multipliers at the second multiplier input.

10. The circuit of claim 6 wherein the second order is the reverse of the first order.

11. A circuit comprising:

a digital data source having an output carrying a sequence of digital signals;

a plurality of delay elements receiving digital signals from the digital data source, the plurality of delay elements having a plurality of outputs, each output carrying a time-shifted version of an adjacent output;

a selection circuit having a plurality of inputs coupled to the plurality of outputs of the delay elements, the selection circuit having a plurality of outputs that carry signals from the plurality of delay elements in a forward time order when a first state is selected and carry signals in a reverse time order when a second state is selected;

a coefficient memory having a plurality of outputs; and

a plurality of multipliers, each multiplier having a first input coupled to an output of the coefficient memory and a second input coupled to an output of the selection circuit.

12. The circuit of claim 11 wherein each of the multipliers further includes an output, each of the multiplier outputs being coupled to a summer.

13. The circuit of claim 11 and further comprising a pre-filter with an input coupled to the output of the digital data source, the pre-filter having a first output coupled an input of a first one of the plurality of delay elements.

14. The circuit of claim 11 wherein plurality of delay elements comprises a first plurality of serially coupled delay elements and a second plurality of serially coupled delay elements, the circuit further comprising a pre-filter coupled to receive the sequence of digital signals, the pre-filter comprising a first output coupled to an input of a first one of the first plurality of serially coupled delay elements and a second output coupled to a first one of the second plurality of serially coupled delay elements.

15. The circuit of claim 14 wherein a sequence of digital signals carried at the first output of the pre-filter is time-shifted relative to a sequence of digital signals carried at the second output of the pre-filter, the time-shift equal to about one half of the period of the sequence of digital signals.

16. An interpolation circuit comprising:

an advance by T/4 filter;

a delay by T/4 filter;

a first register bank having an input coupled to an output of the advance by T/4 filter, the first register bank having a plurality of outputs;

a second register bank having an input coupled to an output of the delay by T/4 filter, the second register bank having a plurality of outputs;

a first select circuit with inputs coupled to the outputs of the first register bank and the outputs of the second register bank, the first select circuit having a plurality of outputs that carry signals derived from a selected subset of the outputs of the first register bank and the outputs of the second register bank;

a second select circuit with inputs coupled to the outputs of the first select circuit, the second select circuit operable to reverse the order of signals provided at its inputs;

a coefficient memory having a plurality of outputs; and

a plurality of multipliers, each multiplier having a first input coupled to an output of the coefficient memory and a second input coupled to an output of the second select circuit.