Hardware emulation of parallel ATA drives with serial ATA interface

• US 6,854,045 B2
• Filed: 06/29/2001
• Issued: 02/08/2005
• Est. Priority Date: 06/29/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ooi, Thien Ern, Gan, Chai Huat, Ooi, Eng Hun
• Primary Examiner(s): Portka, Gary
• Application Number:
  US09/895,691
• Publication Number:
  US 20030005231A1
• Time in Patent Office: 1,320 Days
• Field of Search: 711/111, 711/112, 711/202, 710/62, 710/65, 710/71, 710/72, 710/74
• US Class Current: 711/202
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0674 Disk device

Abstract

An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

Claims

1. An apparatus comprising:

an access detector to detect an access type of an access to one of a plurality of serial ports interfacing to serial storage devices, the access being provided by a parallel driver to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels;

a mapping circuit to map the serial ports to the parallel channels;

a state machine coupled to the access detector and the mapping circuit to emulate a response from the one of the parallel channels based on the access type and the mapped serial ports;

a plurality of registers coupled to the state machine and the access detector to emulate the task file registers of the parallel channels; and

a serial port selector coupled to the state machine and the serial ports to select the one of the serial ports based on the mapped serial ports.

2. The apparatus of claim 1 wherein the access type is one of first, second, third, fourth, and fifth access types.

3. The apparatus of claim 2 wherein the first access type includes a first read to one of a bus master register, a non-data command register, and a device control register, and a first write to one of a bus master register except setting a START bit of bus master command register to a logical one, a non-data command register, and a device control register.

4. The apparatus of claim 3 wherein the state machine comprises:

a first write state to write data to the selected serial port mapped to the one of the parallel channels when the access type is the first write; and

a first read state to read data from the selected serial port mapped to the one of the parallel channels according to a device bit when the access type is the first read.

5. The apparatus of claim 2 wherein the second access type includes one of a second read from and a second write to a device/head register.

6. The apparatus of claim 5 wherein the state machine comprises:

a second write state to write data to the selected serial port mapped to a master parallel channel when the access type is the second write, the second write state inverting a device bit to the selected serial port mapped to a slave parallel channel when the access type is the second write;

a device state to save internally the device bit when the access type is the second write; and

a second read state to read data from the selected serial port mapped to the one of the parallel channel and to return the internally saved device bit when the access type is the second read in a master-slave configuration, the second read state reading from the selected serial port mapped to a master parallel channel and returning the device bit with a logical one when the access type is the second read to a slave parallel channel in a single master configuration.

7. The apparatus of claim 2 wherein the third access type includes a third read to one of a status register, an alternate status register, and an error register of the selected serial port mapped to a slave parallel channel after a power-on or a reset and execution of a device diagnostics command.

8. The apparatus of claim 7 wherein the state machine comprises:

a third read state to read data from the selected serial port mapped to the one of the parallel channels according to a device bit when the access type is the third read.

9. The apparatus of claim 2 wherein the fourth access type includes a fourth read to one of a status register and an alternate status register of the selected serial port mapped to a master parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

10. The apparatus of claim 9 wherein the state machine comprises:

a fourth read state to read data from the selected serial ports mapped to the one of the parallel channels and merge the read data when the access type is the fourth read.

11. The apparatus of claim 10 wherein the fourth read state performs a logical OR operation on the busy (BSY) bits from the read data.

12. The apparatus of claim 10 wherein the fourth read state provides one of first and second codes according to device existence.

13. The apparatus of claim 2 wherein the fifth access type includes a fifth read to an error register of the selected serial port mapped to a master parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

14. The apparatus of claim 13 wherein the state machine comprises:

a fifth read state to read a first error indication from the selected serial port mapped to the master parallel channel and to examine a second error indication of a serial port mapped to a slave parallel channel when the access type is the fifth read, the fifth read state returning an error code according to the first and second error indications of the serial ports mapped to the master and slave parallel channels.

15. The apparatus of claim 14 wherein the fifth read state saves an error indication of the serial port mapped to the slave parallel channel when a device bit is changed to a logical one, the first error indication and the saved error indication being returned as the error code for the serial port mapped to the master parallel channel.

16. The apparatus of claim 2 wherein the state machine comprises:

an interrupt state to generate first and second interrupt signals according to an interrupt bit provided by one of the serial storage devices when the selected serial port is mapped to master and slave parallel channels, respectively.

17. A method comprising:

detecting an access type of an access to one of a plurality of serial ports interfacing to serial storage devices, the access being provided by a parallel driver to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels;

mapping the serial ports to the parallel channels;

emulating a response from the one of the parallel channels based on the access type and the mapped serial ports by a state machine;

emulating the task file registers of the parallel channels; and

selecting the one of the serial ports based on the mapped serial ports.

18. The method of claim 17 wherein the access type is one of first, second, third, fourth, and fifth access types.

19. The method of claim 18 wherein the first access type includes a first read to one of a bus master register, a non-data command register, and a device control register, and a first write to one of a bus master register except setting a START bit of bus master command register to a logical one, a non-data command register, and a device control register.

20. The method of claim 19 wherein emulating the response comprises:

writing data to the selected serial port mapped to the one of the parallel channels when the access type is the first write; and

reading data from the selected serial port mapped to the one of the parallel channels according to a device bit when the access type is the first read.

21. The method of claim 18 wherein the second access type includes one of a second read from and a second write to a device/head register.

22. The method of claim 21 wherein emulating the response comprises:

writing data to the selected serial port mapped to a master parallel channel when the access type is the second write;

inverting a device bit to the selected serial port mapped to a slave parallel channel when the access type is the second write;

saving internally the device bit when the access type is the second write; and

reading data from the selected serial port mapped to the one of the parallel channel;

returning the internally saved device bit when the access type is the second read in a master-slave configuration; and

reading from the selected serial port mapped to a master parallel channel and returning the device bit with a logical one when the access type is the second read to a slave parallel channel in a single master configuration.

23. The method of claim 18 wherein the third access type includes a third read to one of a status register, an alternate status register, and an error register of the selected serial port mapped to a slave parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

24. The method of claim 23 wherein emulating the response comprises:

reading data from the selected serial port mapped to the one of the parallel channels according to a device bit when the access type is the third read.

25. The method of claim 18 wherein the fourth access type includes a fourth read to one of a status register and an alternate status register of the selected serial port mapped to a master parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

26. The method of claim 25 wherein emulating the response comprises:

reading data from the selected serial ports mapped to the one of the parallel channels and merging the read data when the access type is the fourth read.

27. The method of claim 26 wherein reading data when the access type is the fourth read comprises performing a logical OR operation on the busy (BSY) bits from the read data.

28. The method of claim 26 wherein reading data when the access type is the fourth read comprises providing one of first and second codes according to device existence.

29. The method of claim 18 wherein the fifth access type includes a fifth read to an error register of the selected serial port mapped to a master parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

30. The method of claim 29 wherein emulating the response comprises:

reading a first error indication from the selected serial port mapped to the master parallel channel when the access type is the fifth read;

examining a second error indication of a serial port mapped to a slave parallel channel when the access type is the fifth read;

returning an error code according to the first and second error indications of the serial ports mapped to the master and slave parallel channels.

31. The method of claim 30 wherein emulating the response further comprises:

saving an error indication of the serial port mapped to the slave parallel channel when a device bit is changed to a logical one and the access type is the fifth read; and

returning the error code according to the first and the saved error indications to the serial port mapped to the master parallel channel when the access type is the fifth read.

32. The method of claim 17 wherein emulating the response comprises:

generating first and second interrupt signals according to an interrupt bit provided by one of the serial storage devices when the selected serial port is mapped to master and slave parallel channels, respectively.

33. A system comprising:

a plurality of serial storage devices; and

a chipset coupled to the serial storage devices, the chipset having a serial storage controller, the serial storage controller comprising;

an access detector to detect an access type of an access to one of a plurality of serial ports interfacing to the serial storage devices, the access being provided by a parallel driver to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels,

a mapping circuit to map the serial ports to the parallel channels,

a state machine coupled to the access detector and the mapping circuit to emulate a response from the one of the parallel channels based on the access type and the mapped serial ports;

a plurality of registers coupled to the state machine and the access detector to emulate the task file registers of the parallel channels; and

a serial port selector coupled to the state machine and the serial ports to select the one of the serial ports based on the mapped serial ports.

34. The system of claim 33 wherein the access type is one of first, second, third, fourth, and fifth access types.

35. The system of claim 34 wherein the first access type includes a first read to one of a bus master register, a non-data command register, and a device control register, and a first write to one of a bus master register except setting a START bit of bus master command register to a logical one, a non-data command register, and a device control register.

36. The system of claim 35 wherein the state machine comprises:

a first write state to write data to the selected serial port mapped to the one of the parallel channels when the access type is the first write; and

a first read state to read data from the selected serial port mapped to the one of the parallel channels according to a device bit when the access type is the first read.

37. The system of claim 34 wherein the second access type includes one of a second read from and a second write to a device/head register.

38. The system of claim 37 wherein the state machine comprises:

a second write state to write data to the selected serial port mapped to a master parallel channel when the access type is the second write, the second write state inverting a device bit to the selected serial port mapped to a slave parallel channel when the access type is the second write;

a device state to save internally the device bit when the access type is the second write; and

a second read state to read data from the selected serial port mapped to the one of the parallel channel and to return the internally saved device bit when the access type is the second read in a master-slave configuration, the second read state reading from the selected serial port mapped to a master parallel channel and returning the device bit with a logical one when the access type is the second read to a slave parallel channel in a single master configuration.

39. The system of claim 34 wherein the third access type includes a third read to one of a status register, an alternate status register, and an error register of the selected serial port mapped to a slave parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

40. The system of claim 39 wherein the state machine comprises:

a third read state to read data from the selected serial port mapped to the one of the parallel channels according to a device bit when the access type is the third read.

41. The system of claim 34 wherein the fourth access type includes a fourth read to one of a status register and an alternate status register of the selected serial port mapped to a master parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

42. The system of claim 41 wherein the state machine comprises:

a fourth read state to read data from the selected serial ports mapped to the one of the parallel channels and merge the read data when the access type is the fourth read.

43. The system of claim 42 wherein the fourth read state performs a logical OR operation on the busy (BSY) bits from the read data.

44. The system of claim 42 wherein the fourth read state provides one of first and second codes according to device existence.

45. The system of claim 34 wherein the fifth access type includes a fifth read to an error register of the selected serial port mapped to a master parallel channel after a power-on or a reset and execution of an Execute Device Diagnostics command.

46. The system of claim 45 wherein the state machine comprises:

a fifth read state to read a first error indication from the selected serial port mapped to the master parallel channel and to examine a second error indication of a serial port mapped to a slave parallel channel when the access type is the fifth read, the fifth read state returning an error code according to the first and second error indications of the serial ports mapped to the master and slave parallel channels.

47. The system of claim 46 wherein the fifth read state saves an error indication of the serial port mapped to the slave parallel channel when a device bit is changed to a logical one, the first error indication and the saved error indication being returned as the error code for the serial port mapped to the master parallel channel.

48. The system of claim 33 wherein the state machine comprises:

an interrupt state to generate first and second interrupt signals according to an interrupt bit provided by one of the serial storage devices when the selected serial port is mapped to master and slave parallel channels, respectively.