Castellation wafer level packaging of integrated circuit chips

• US 6,855,572 B2
• Filed: 08/28/2002
• Issued: 02/15/2005
• Est. Priority Date: 08/28/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Loo, Neo Yong, Koon, Eng Meow, Kwang, Chua Swee, Waf, Low Siu, Wei, Zhou, Wu, Huang Shuang
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/233,149
• Publication Number:
  US 20040043535A1
• Time in Patent Office: 902 Days
• Field of Search: 438/106, 438/107, 438/108, 438/109, 438/110, 438/113, 438/598
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Claims

1. A method of packaging and stacking integrated circuit chips fabricated on a same wafer, each of the integrated circuit chips having active circuit areas, the method comprising:

coupling active circuit areas of a first integrated circuit chip on a wafer to active circuit areas of a second integrated circuit chip on the wafer with a plurality of first electrical contacts;

coupling a plurality of second electrical contacts to and on top of the plurality of first electrical contacts wherein the second electrical contacts are substantially thicker than the first contacts and are positioned between the first and second chips;

encapsulating the second electrical contacts such that the top surfaces of the second electrical contacts are left exposed;

cutting the wafer through the second electrical contacts between the first and second chips, the first and second chips being separated, the second electrical contacts having exposed top and side surfaces; and

stacking the first integrated circuit chip over the second integrated circuit chip such that (1) the active circuit areas of the first integrated circuit chip are in a plane substantially parallel to the active circuit areas of the second integrated circuit chip, and (2) the corresponding second electrical contacts of the first and second integrated circuit chips are in the same plane.

2. The method of claim 1 wherein the first electrical contacts are selected from the group consisting of aluminum, copper, under bump material, and combinations thereof.

3. The method of claim 1 wherein the second electrical contacts are selected from the group consisting of aluminum, copper, under bump material, and combinations thereof.

4. The method of claim 1, wherein the second electrical contacts are castellation blocks.

5. The method of claim 1, wherein the encapsulant is selected from the group consisting of an epoxy molding compound, a liquid type epoxy, a liquid encapsulant, SU-8, and combinations thereof.

6. The method of claim 1, further comprising coupling the second electrical contacts of the first integrated circuit chip to the second electrical contacts of the second integrated circuit chip with third electrical contacts, wherein the third electrical contacts comprise solder.

7. The method of claim 1 wherein the first electrical contacts are coupled to the active circuit areas of the first chip by a plurality of third electrical contacts.

8. The method of claim 7 wherein the first electrical contacts are coupled to the active circuit areas of the second chip by a plurality of fourth electrical contacts.

9. The method of claim 8 wherein the fourth electrical contact is an extension of the first electrical contact.

10. The method of claim 1 further comprising depositing under bump material on a portion of the first electrical contacts when the first electrical contacts are other than under bump material.

11. The method of claim 1 wherein said cutting comprises using a dicing blade.

12. The method of claim 11 further comprising cutting a portion of the encapsulant.

13. The method of claim 1 wherein the cutting comprises sawing a portion of the wafer between the first and second chips.

14. The method of claim 13 wherein the cutting further comprises thinning a portion of the wafer on the side opposite the side on which the first and second electrical contacts are located.

15. The method of claim 1 wherein each chip is adapted to be written to and read from.

16. The method of claim 15 wherein information is written to or read from a respective one of said chips when that respective chip is activated.

17. The method of claim 16 further comprising activating said respective one of said chips in response to an activation signal.

18. The method of claim 17 wherein the activation signal is a “

code”

or “

key”

signal.

19. The method of claim 17 wherein the activation signal is applied to at least one second electrical contact of a packaged chip.

20. The method of claim 19 wherein the activation signal is a signal selected from the group consisting of a binary code, an analog signal, and combinations thereof.

21. The method of claim 1 further comprising coupling the first integrated circuit chip and second integrated circuit chip to a device that can write information to and read information from the first integrated circuit chip and the second integrated circuit chip.

22. The method of claim 21 wherein the device is a motherboard.

23. The method of claim 21 further comprising coupling the device to the first integrated circuit chip and second integrated circuit chip via a motherboard.

24. The method of claim 1 further comprising coupling the first integrated circuit chip to a sensor selected from the group consisting of photo-sensors, pressure sensors, chemical/gas sensors, and combinations thereof.

25. The method of claims 24 wherein the sensor is a photo-sensor, the method further comprising using a lens/optical endcap to focus light on the photo-sensor.

26. The method of claim 24 wherein the photo-sensor is adapted to generate signals in response to sensing light.

27. The method of claim 26 wherein the light is infrared light or ultra-violet light.

28. The method of claim 1 further comprising coupling input/output pads to the second electrical contacts.

29. The method of claim 1 further comprising coupling the second electrical contacts of the integrated circuit chips to a printed circuit board.

30. The method of claim 29 wherein the printed circuit board has electrical contacts printed on a face of the board, said method further comprising coupling the second electrical contacts to the electrical contacts.

31. A method of packaging and stacking integrated circuit chips, the integrated circuit chips each having active circuit areas, the method comprising:

coupling a first electrical contact to an active circuit area of a first integrated circuit chip on a wafer;

coupling a second electrical contact to the first electrical contact wherein the second electrical contact is (a) large enough to be electrically coupled to solder, anisotropic conductive film, or anisotropic conductive paste, and (b) substantially encapsulated by an encapsulant;

coupling a third electrical contact to an active circuit area of a second integrated circuit chip on the wafer;

coupling a fourth electrical contact to the third electrical contact wherein the fourth electrical contact is (1) large enough to be electrically coupled to under bump material, and (2) substantially encapsulated by an encapsulant;

separating the wafer into two portions such that one portion includes the first chip and the other portion includes the second chip;

stacking the first chip over the second chip such that (i) the active circuit area of the first chip is in a plane substantially parallel to the active circuit area of the second chip, and (ii) the second electrical contact and the fourth electrical contact are in the same plane; and

coupling the second electrical contact and the fourth electrical contact with a fifth electrical contact, the fifth electrical contact being on the inside face of a printed circuit board which is in a plane substantially perpendicular to the plane of the active circuit area of the first chip.

32. The method of claim 31 wherein the first and third electrical contacts are selected from the group consisting of aluminum, copper, under bump material, and combinations thereof.

33. The method of claim 31 wherein the second and fourth electrical contacts are selected from the group consisting of aluminum, copper, and combinations thereof.

34. The method of claim 31 wherein the second and fourth electrical contacts are castellation blocks.

35. The method of claim 31 wherein the encapsulant is selected from the group consisting of an epoxy molding compound, a liquid type epoxy, a liquid encapsulant, SU-8, and combinations thereof.

36. The method of claim 31 wherein the fifth electrical contact comprises solder.

37. The method of claim 31 further comprising depositing under bump material on the first and third electrical contacts when the first and third electrical contact are other than under bump material.

38. The method of claim 31 wherein the top surfaces of the second and fourth electrical contacts are left exposed by the encapsulant.

39. The method of claim 31 wherein the separating comprises thinning a portion of the wafer on the side of the wafer opposite the side on which the first and third electrical contacts era located.

40. The method of claim 31 wherein each chip is adapted to be written to and read from.

41. The method of claim 40 wherein information is written to or read from each chip when that chip is activated.

42.The method of claim 41 further comprising activating a chip in response to an activation signal.

44. The method of claim 31 further comprising coupling the first integrated circuit chip and second integrated circuit chip to a device that can write information to and read information from the first integrated circuit chip and the second integrated circuit chip.

47. The method of claim 31 further comprising coupling input/output pads to the second and fourth electrical contacts.

42. The method of claim 42 further comprising activating the chip in response to an activation signal applied to the second electrical contact.

43. The method of claim 42 further comprising activating the first chip in response to an activation signal applied to the second electrical contact.

45. The method of claim 45 wherein the device is a motherboard.

46. The method of claim 45 further comprising coupling the device to the first integrated circuit chip and second integrated circuit chip via a motherboard.

48. A method for packaging and stacking integrated circuit chips, each of the integrated circuit chips having active circuit areas, the method comprising:

depositing first and second integrated circuit chips on a wafer;

depositing a first electrical contact large enough to be electrically coupled to solder, anisotropic conductive film, or anisotropic conductive paste on the wafer between the first and second chips;

encapsulating the first electrical contacts with an encapsulant such that the top surfaces of the first electrical contacts are left exposed;

coupling an active circuit area of the first chip to one of the first electrical contacts with a second electrical contact;

coupling an active circuit area of the second chip to one of the first electrical contacts with a third electrical contact;

cutting the wafer through the encapsulant and first electrical contacts between the first and second chips to separate the wafer into a first wafer portion arid a second wafer portion, the first wafer portion including the first integrated circuit chip and the second wafer portion including the second integrated circuit chip, the cutting exposing a side face of the cut first electrical contacts; and

stacking the first wafer portion over the second wafer portion such that the active circuit area of the first integrated circuit chip is in a plane substantially parallel to the active circuit area of the second integrated circuit chip.

49. The method of claim 49 wherein the first electrical contact is a castellation block.

50. The method of claim 49 wherein said cutting comprises using a dicing blade or laser machining techniques.

51. The method of claim 49 further comprising coupling an input/output pad to the first electrical contact.

52. The method of claim 49 wherein each chip is adapted to be written to and read from.

59. The method of claim 49 further comprising coupling the first integrated circuit chip and second integrated circuit chip to a device that can write information to and read information from the first integrated circuit chip and the second integrated circuit chip.

53. The method of claim 53 wherein information is written to or read from a respective one of said chips when that chip is activated.

54. The method of claim 54 further comprising activating said respective one of said chips in response to an activation signal.

55. The method of claim 55 further comprising applying the activation signal to a portion of a first electrical contact coupled to an integrated circuit chip.

56. The method of claim 56 wherein the activation signal is a “

code”

or “

key”

signal.

57. The method of claim 56 wherein there is more than one first electrical contact coupled to each integrated circuit chip, said method further comprising applying the activation signal to more than one first electrical contact.

58. The method of claim 58 wherein the activation signal is a signal selected from the group consisting of a binary code, an analog signal, and combinations thereof.

60. The method of claim 60 wherein the device is a motherboard.

61. The method of claim 61 further comprising coupling the device to the first integrated circuit chip and second integrated circuit chip via a motherboard.