Trench-gate semiconductor devices, and their manufacture

• US 6,855,601 B2
• Filed: 12/11/2003
• Issued: 02/15/2005
• Est. Priority Date: 07/24/2001
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Gajda, Mark A.
• Primary Examiner(s): Brewster, William M.
• Application Number:
  US10/733,214
• Publication Number:
  US 20040124461A1
• Time in Patent Office: 432 Days
• Field of Search: 438/259, 438/268, 438/270, 438/271
• US Class Current: 438/259
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a). The height (z) of this silicide protrusion can be defined by a layer thickness of a mask (51,52; 510,520) with a window (51a, 510a) at which the trench (20) is etched. The silicide material may be deposited or grown in situ by alloying.

Claims

1. A method of manufacturing a trench-gate semiconductor device having source and drain regions which are separated by a channel-accommodating region adjacent to the trench-gate, including the following sequence of steps:

(a) providing at a surface of a semiconductor body a masking pattern having therein a window that is used for self-aligning a gate trench and parts of the gate formed in the subsequent steps (b) to (d);

(b) etching the trench into the semiconductor body within the window, and forming a dielectric layer at the walls of the trench to provide a gate dielectric for capacitively coupling the gate to the channel-accommodating region,

(c) depositing and then etching back semiconductor gate material to provide a semiconductor gate part on the dielectric layer in the trench without protruding above the masking pattern at the window, and

(d) then providing at the window a thickness of metal silicide material at the top of the semiconductor gate part sufficient to form a silicide upstanding part of the gate having a top and sidewalls that protrude upward above the level of the body surface, the gate dielectric at least adjacent to the channel-accommodating region being protected from the metal silicide material by at least the semiconductor part of the gate and by the protrusion of its silicide part above the level of the body surface.

2. A method according to claim 1, wherein the said window of the masking pattern provided in step (a) is a wide window that is narrowed to a narrower window by providing sidewall extensions at the sidewalls of the wide window, the trench is etched in step (b) at the narrower window, and the source region is provided so as to be self-aligned with the trench-gate by means of these sidewall extensions.

3. A method according to claim 1, wherein, after the step (c), the following steps are carried out:

sidewall extensions are provided at sidewalls of the window of step (a) to form a further window that is narrower than the width of the trench,

the metal silicide material is deposited in the said further window in step (d) so as to form the silicide upstanding part of the trench-gate spaced from the walls of the trench,

an insulating overlayer is provided over the silicide upstanding part of the trench-gate,

and the masking pattern is then removed before providing a source electrode to contact the source region and to extend over the insulating overlayer over the trench-gate.

4. A method according to claim 1, wherein the semiconductor gate material provided in the trench in step (c) comprises polycrystalline silicon protruding above the level of the body surface, sidewalls of the protruding polycrystalline silicon are exposed, and a silicide-forming metal is then deposited on the protruding polycrystalline silicon and is alloyed into the sidewalls and top of the protruding polycrystalline silicon so as to form the silicide upstanding part on top of remaining silicon semiconductor gate material in the trench.

8. A method according to claim 4, wherein the deposited silicide-forming metal is heated by rapid thermal annealing to form the silicide with the silicon gate material.

9. A method according to claim 1, wherein the surface of the metal silicide upstanding part is subsequently oxidised so as to grow an insulating oxide adjacent to the silicide, which insulating oxide forms at least a part of an insulating over-layer provided over the top of the protruding part of the trench-gate, and a source electrode is deposited on the insulating over-layer and on an exposed surface area of the semiconductor body beside the trench-gate after removing the lower layer of the masking pattern.

10. A method according to claim 9, wherein the masking pattern includes a silicon nitride layer that is used to mask the underlying body surface from oxidation during the growth of the insulating oxide adjacent to the silicide.

5. A method of manufacturing a trench-gate semiconductor device having source and drain regions which are separated by a channel-accommodating region adjacent to the trench-gate, including the following sequence of steps:

(a) providing at a surface of a semiconductor body a masking pattern comprising upper and lower layers through which a window extends at an area of the body where the trench-gate is to be provided,

(b) etching a trench for the gate into the body at the window, and forming a gate dielectric layer at the walls of the trench in the semiconductor body,

(c) providing silicon gate material in the trench and in the window, and then removing the upper layer of the masking pattern such that the silicon gate material has an upstanding upper part that protrudes above the adjacent surface of the lower layer of the masking pattern,

(d) depositing a silicide-forming metal over the silicon gate material and over the lower layer of the masking pattern, and heating at least the metal to grow a metal silicide into the silicon gate material from the top and side-walls of the upstanding upper part, and

(e) removing the un-silicided metal so as to leave a partially-silicided trench-gate protruding from the semiconductor body.

6. A method according to claim 5, wherein the upper layer of the masking pattern is thicker, for example at least 5 times thicker, than the lower layer.

7. A method according to claim 5, wherein the upper layer of the masking pattern comprises silicon dioxide, and the lower layer comprises silicon nitride on a thinner layer of silicon dioxide on the semiconductor body surface.