Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof

• US 6,855,603 B2
• Filed: 03/14/2003
• Issued: 02/15/2005
• Est. Priority Date: 06/27/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Young-hee, Choi, Won-bong, Lee, Jo-won
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROCCHEGIANI, RENZO
• Application Number:
  US10/387,561
• Publication Number:
  US 20030227015A1
• Time in Patent Office: 704 Days
• Field of Search: 438/156, 438/158, 438/173, 438/192, 438/206, 438/212, 438/268, 438/270, 257/135, 257/302, 257261-263
• US Class Current: 438/268
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/17 Memory cell being a nanowire transistor
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/708 with distinct switching device
• CPC Class Codes: Y10S 977/723 On an electrically insulating substrate
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/843 Gas phase catalytic growth, i.e. chemical vapor deposition
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Claims

1. A method of manufacturing a vertical nano-sized transistor using carbon nanotubes, comprising:

(a) forming sources on a semiconductor substrate;

(b) forming an insulating layer using a nonconductor material and forming holes having nano-sized diameters in the insulating layer at portions of the insulating layer corresponding to the sources, where the holes are spaced at intervals of several nanometers;

(c) vertically growing carbon nanotubes on the sources in the holes;

(d) forming gates in the vicinity of the carbon nanotubes;

(e) depositing a nonconductor film over the gates to till the holes; and

(f) forming drains over the nonconductor film and the carbon nanotubes.

2. The method according to claim 1, wherein while forming the insulating layer, the nonconductor material is one selected from the group consisting of Al₂O₃ and Si.

3. The method according to claim 1, wherein vertically growing carbon nanotubes is performed by one method selected from chemical vapor deposition, electrophoresis and mechanical compression.