Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor

• US 6,855,954 B1
• Filed: 07/19/2000
• Issued: 02/15/2005
• Est. Priority Date: 10/18/1999
• Status: Expired due to Term

• Current Assignee: Unified Innovative Technology, LLC (LG Display Co., Ltd.)
• Original Assignee: Fujitsu Display Technologies Corporation (Fujitsu Limited)
• Inventors: Zhang, Hong Yong
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/619,556
• Time in Patent Office: 1,672 Days
• Field of Search: 257/9, 257/57, 257/59, 257/66, 257/67, 257/72, 438/149, 438/151, 438/157, 438/166, 438/152, 438/48, 438/128, 438/283
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

The present invention relates to a thin film transistor, a fabrication method thereof and a liquid crystal display having the thin film transistor, and an object of the present invention is to provide a thin film transistor which improves a fabrication yield, a fabrication method thereof and a liquid crystal display having the thin film transistor. In a bottom-gate-type thin film transistor 1 having a gate electrode 4 formed on a substrate, a gate insulating film 6 formed on the gate electrode, an operational semiconductor film 8 formed on the gate insulating film 6 on the gate electrode 4, a channel protection film 3 formed on the operational semiconductor film, and a source and a drain electrodes 14 and 15 formed on both sides of the top surface of the channel protection film 3 connected to the operational semiconductor film with the operational semiconductor, and the channel protection film 3 has a first insulating layer 10 contacting to an upper interface of the operational semiconductor film 8 and a second insulating layer 11 formed on the first insulating layer.

Claims

1. A bottom gate type thin film transistor comprising:

a gate electrode formed on a substrate;

a gate insulating film formed on the gate electrode;

an operational semiconductor film formed on the gate insulating film on the gate electrode;

a channel protection film formed on the operational semiconductor film;

a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film; and

the channel protection film including a first insulating layer that contacts an upper surface of the operational semiconductor film, and a second insulating layer formed on the first insulating layer;

wherein a dielectric constant of the second insulating layer is less than or equal to the dielectric constant of the first insulating layer;

a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer; and

a width of the second insulating layer is less than a width of said first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.

2. A thin film transistor comprising:

a gate electrode formed on a substrate;

a gate insulating film formed on the gate electrode;

an operational semiconductor film formed on the gate insulating film on the gate electrode;

a channel protection film formed on the operational semiconductor film;

a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film; and

the channel protection film including a first insulating layer that contacts an upper surface of the operational semiconductor film and a second insulating layer formed on the first insulating layer,

wherein a dielectric constant of the second insulating layer is less than or equal to the dielectric constant of the first insulating layer;

a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer; and

a width of the second insulating layer is less than a width of said first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.

3. A method of fabricating a bottom gate type thin film transistor comprising:

forming a gate electrode on a substrate;

forming a gate insulating film on the gate electrode;

forming an operational semiconductor film on the gate insulating film on the gate electrode;

forming a channel protection film on the operational semiconductor film, wherein the channel protection film is formed by laminating a first insulating layer to contact an upper surface of the operational semiconductor film and by laminating a second insulating layer on the first insulating layer;

reducing the parasitic capacitance formed by the channel protection film by;

selecting materials for the first and second insulating layers such that said second insulating layer has a dielectric constant that is less than or equal to the dielectric constant of the first insulating layer;

selecting the thickness of the first insulating layer to be within the range of approximately 100-300 nm, and selecting the thickness of the second insulating layer to be is greater than or equal to the thickness of the first insulating layer;

forming a source electrode and a drain electrode on each side, respectively, of a top surface of the channel protection film, and connecting said source and drain electrodes to the operational semiconductor film; and

making the second insulating layer of a narrower width than the first insulating layer and forming light doping drain (LDD) areas on the operational semiconductor film by using the second insulating layer as a shield.

4. An active matrix type liquid crystal display comprising:

a plurality of gate wirings formed on a substrate;

a plurality of data wirings arranged perpendicular to the gate wirings; and

a thin film transistor formed for each of a plurality of pixel areas defined by the plurality of gate wirings and the plurality of data wirings,

wherein the thin film transistor includes a gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, an operational semiconductor film formed on the gate insulating film on the gate electrode, a channel protection film formed on the operational semiconductor film, and a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film, and

wherein the channel protection film includes a first insulating layer contacting an upper surface of the operational semiconductor film and a second insulating layer formed on the first insulating layer

a dielectric constant of the second insulating layer is less than or equal to the dielectric constant of the first insulating layer;

a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer; and

the second insulating layer is less than a width of the first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.

5. A bottom gate type thin film transistor comprising:

a gate electrode formed on a substrate;

a gate insulating film formed on the gate electrode;

an operational semiconductor film formed on the gate insulating film on the gate electrode;

a channel protection film formed on the operational semiconductor film;

a source electrode and a drain electrode formed, respectively, on each side of a top surface of the channel protection film and being connected to the operational semiconductor film; and

the channel protection film including a first insulating layer that contacts an upper surface of the operational semiconductor film and a second insulating layer formed on the first insulating layer;

wherein a thickness of the first insulating layer is within the range of approximately 100-300 nm, and a thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer; and

a width of the second insulating layer is less than a width of the first insulating layer, such that light doping drain (LDD) areas can be formed on the operational semiconductor film.