Structure and method for fabricating configurable transistor devices utilizing the formation of a compliant substrate for materials used to form the same
First Claim
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1. A semiconductor structure comprising:
- a) a monocrystalline Group IV substrate;
b) a layer of amorphous oxide of Group IV in contact with said substrate;
c) a monocrystalline metal oxide and/or metal nitride layer overlying the amorphous layer;
d) a metal or metal oxide capping layer in contact with said monocrystalline metal oxide and/or metal nitride layer;
e) a compound semiconductor template layer in contact with said capping layer; and
f) a monocrystalline compound semiconductor layer in contact with said template layer; and
a composite transistor comprising a first transistor having first active regions formed at least in part in a silicon portion of the semiconductor structure, a second transistor having second active regions formed at least in part in a monocrystalline compound semiconductor portion of the semiconductor structure, and a mode control terminal for controlling the first transistor and the second transistor.
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Abstract
A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material. A composite transistor includes a first transistor having first active regions formed in the monocrystalline silicon substrate, a second transistor having second active regions formed in the monocrystalline compound semiconductor material, and a mode control terminal for controlling the first transistor and the second transistor.
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Citations
28 Claims
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1. A semiconductor structure comprising:
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a) a monocrystalline Group IV substrate;
b) a layer of amorphous oxide of Group IV in contact with said substrate;
c) a monocrystalline metal oxide and/or metal nitride layer overlying the amorphous layer;
d) a metal or metal oxide capping layer in contact with said monocrystalline metal oxide and/or metal nitride layer;
e) a compound semiconductor template layer in contact with said capping layer; and
f) a monocrystalline compound semiconductor layer in contact with said template layer; and
a composite transistor comprising a first transistor having first active regions formed at least in part in a silicon portion of the semiconductor structure, a second transistor having second active regions formed at least in part in a monocrystalline compound semiconductor portion of the semiconductor structure, and a mode control terminal for controlling the first transistor and the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor structure comprising:
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a) a monocrystalline Group IV substrate;
b) a layer of amorphous oxide of Group IV in contact with said substrate;
c) a monocrystalline metal oxide and/or metal nitride layer overlying the amorphous layer;
d) a metal or metal oxide capping layer in contact with said monocrystalline metal oxide and/or metal nitride layer;
e) a compound semiconductor template layer in contact with said capping layer; and
f) a monocrystalline compound semiconductor layer in contact with said template layer;
a silicon transistor formed at least in part in the monocrystalline silicon substrate;
a compound transistor formed at least in part in the monocrystalline compound semiconductor material;
a switch to selectively couple the silicon transistor and the compound transistor in response to a control signal; and
a control circuit configured to provide the control signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor structure comprising:
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a) a monocrystalline Group IV substrate;
b) a layer of amorphous oxide of Group IV in contact with said substrate;
c) a monocrystalline metal oxide and/or metal nitride layer overlying the amorphous layer;
d) a metal or metal oxide capping layer in contact with said monocrystalline metal oxide and/or metal nitride layer;
e) a compound semiconductor template layer in contact with said capping layer; and
f) a monocrystalline compound semiconductor layer in contact with said template layer;
one or more silicon transistors formed at least in part in the monocrystalline silicon substrate;
one or more compound transistors formed at least in part in the monocrystalline compound semiconductor material; and
switches associated with respective transistors of the one or more silicon transistors and the one or more compound transistors, the switches receiving control signals for selectively coupling the respective transistors to one of the signal input circuit and the signal output circuit. - View Dependent Claims (23, 24, 25)
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26. A semiconductor structure comprising:
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a) a monocrystalline Group IV substrate;
b) a layer of amorphous oxide of Group IV in contact with said substrate;
c) a monocrystalline metal oxide and/or metal nitride layer overlying the amorphous layer;
d) a metal or metal oxide capping layer in contact with said monocrystalline metal oxide and/or metal nitride layer;
e) a compound semiconductor template layer in contact with said capping layer; and
f) a monocrystalline compound semiconductor layer in contact with said template layer;
at least one configurable transistor formed at least in part in the monocrystalline compound semiconductor material; and
a control circuit electrically coupled with the transistor and formed at least in part in a silicon portion of the semiconductor structure. - View Dependent Claims (27, 28)
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Specification