Maximum VCC calculation method for hot carrier qualification

• US 6,856,160 B1
• Filed: 06/10/2002
• Issued: 02/15/2005
• Est. Priority Date: 06/10/2002
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Marathe, Amit P., Yang, Nian, Yang, Tien-Chun, Kim, Hyeon-Seag
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US10/166,105
• Time in Patent Office: 981 Days
• Field of Search: 324/765, 324/766, 324/769, 438/17, 702/182, 714/1, 714/47
• US Class Current: 324/762.09
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

A method of generating an operating condition projection corresponding to a predetermined lifetime for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition by inducing a predetermined drain-source voltage for each stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

Claims

1. A method of generating a lifetime projection for semiconductor devices, comprising:

collecting device lifetime information for a plurality of semiconductor devices at more than one stress condition, the stress condition being based on an induced drain-source voltage stress condition;

calculating, for each stress condition, a lifetime level at which a predetermined percentage of devices will exceed, each lifetime level being a data point on the stress condition versus lifetime graph;

calculating the slope of an interpolated line through the data points on the stress condition versus lifetime graph; and

determining a line corresponding to a ratio of substrate current to gate current versus drain voltage relationship that satisfies the lifetime level, based on the interpolated line information.

2. The method of claim 1, further comprising:

calculating the ratio of substrate current to gate current at operating conditions for a fabricated device.

3. The method of claim 2, further comprising:

determining the maximum drain-source voltage to achieve a predetermined lifetime.

4. The method of claim 2, further comprising:

determining the lifetime for the fabricated device.

5. The method of claim 1, wherein the devices include n-type metal oxide semiconductor devices.

6. The method of claim 1, wherein the devices include p-type metal oxide semiconductor devices.

7. The method of claim 1, wherein the predetermined percentage of devices is at least 90 percent.

8. The method of claim 1, wherein the predetermined percentage of devices is at least 99 percent.

9. The method of claim 1, wherein the predetermined percentage of devices is at least 99.9 percent.