Versatile system for high resolution device calibration

• US 6,856,174 B1
• Filed: 10/01/2003
• Issued: 02/15/2005
• Est. Priority Date: 10/01/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bellaouar, Abdellatif, Fontaine, Paul H.
• Primary Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/677,105
• Time in Patent Office: 503 Days
• Field of Search: 327/100, 327/141, 341/143, 341/144, 341/118, 341/120
• US Class Current: 327/100
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: H03M 1/1014 at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits

Abstract

The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the programmable semiconductor component, within a desired accuracy, to a goal value (802). The system provides a primary DAC function (510) and a supplemental DAC function (512), as well as a control function (506). The control function is utilized to determine a first bit step (806) of the primary DAC function that corresponds to the goal value. The control function then determines a second bit step (810) of the supplemental DAC function that corresponds to the goal value. The bit codes of the first and second bit steps are combined by a summing function (514), to provide a programming control word for the programmable semiconductor component.

Claims

1. A semiconductor device comprising:

an analog reference signal;

a comparator function communicatively coupled to the analog reference signal;

a controller communicatively coupled to the comparator function;

a primary DAC function communicatively coupled to a state machine and to a summer;

a supplemental DAC communicatively coupled to the state machine and to the summer; and

a target component communicatively coupled to the summer and the comparator.

2. The device of claim 1, wherein the analog reference signal comprises a bandgap voltage.

3. The device of claim 1, wherein the analog reference signal comprises a clock signal.

4. The device of claim 1, wherein the comparator comprises an independent device.

5. The device of claim 1, wherein the comparator comprises a sub-portion of another device.

6. The device of claim 1, wherein the comparator comprises a combination of hardware and software.

7. The device of claim 1, wherein the controller comprises a state machine function.

8. The device of claim 1, wherein controller comprises a programmable logic device.

9. The device of claim 1, wherein the controller comprises a code segment operating on a processor.

10. The device of claim 1, wherein the primary DAC comprises an independent DAC device.

11. The device of claim 1, wherein the primary DAC comprises a sub-portion of a DAC device.

12. The device of claim 1, wherein the primary DAC comprises a code segment operating on a processor.

13. The device of claim 1, wherein the supplemental DAC comprises an independent DAC device.

14. The device of claim 1, wherein the supplemental DAC comprises a sub-portion of a DAC device.

15. The device of claim 1, wherein the supplemental DAC comprises a code segment operating on a processor.

16. The device of claim 1, wherein the summer comprises an independent device.

17. The device of claim 1, wherein the summer comprises a sub-portion of another device.

18. The device of claim 1, wherein the summer comprises a code segment operating on a processor.

19. The device of claim 1, wherein the target component comprises a programmable array.

20. The device of claim 19, wherein the target component comprises a programmable resistor array.

21. The device of claim 19, wherein the target component comprises a programmable capacitor array.

22. The device of claim 19, wherein the target component comprises a programmable inductor array.

23. A method of providing high-resolution calibration of a programmable semiconductor component, the method comprising the steps of:

providing a programmable semiconductor component;

providing a goal value for the programmable semiconductor component;

providing primary and supplemental DAC functions;

providing a control function;

utilizing the control function to determine a first bit step of the primary DAC function corresponding to the goal value;

utilizing the control function to determine a second bit step of the supplemental DAC function corresponding to the goal value; and

combining bit codes of the first and second bit steps to provide a control word for programming the programmable semiconductor component.

24. The method of claim 23, further comprising the steps of:

providing a reference signal;

determining a differential between the reference signal and a programmed value of the programmable semiconductor component; and

communicating the differential to the control function.

25. The method of claim 24, wherein the steps of determining a differential, communicating the differential, utilizing the control function, and combining bit codes to provide a control word are performed as part of an iterative process.

26. The method of claim 23, wherein a plurality of supplemental DAC function are provided and the control function is utilized to determine bits steps for each, sequentially.

27. The method of claim 23, wherein the control function utilizes a dichotomy algorithm.

28. The method of claim 23, wherein the control function utilizes an incremental parsing algorithm.