Sub-micron high input voltage tolerant input output (I/O) circuit

• US 6,856,176 B2
• Filed: 07/16/2003
• Issued: 02/15/2005
• Est. Priority Date: 01/09/2001
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US10/621,008
• Publication Number:
  US 20040017230A1
• Time in Patent Office: 580 Days
• Field of Search: 327/333, 327/112, 327/108, 327/379, 327/382, 327/387, 327/389, 326/62, 326/63, 326/65, 326/80, 326/81, 326/82, 326/83, 326/86, 326/87
• US Class Current: 327/108
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices coupled between a power supply (V_DDO) and an I/O pad;

a lower pair of N-channel MOS devices (NMOS), coupled between the I/O pad and a ground potential;

a first bias circuit providing a first bias voltage to the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit providing a second bias voltage to the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit providing a first fixed voltage to the second upper PMOS device when V_PAD is less than the V_DDO voltage and a voltage equal to V_PAD otherwise; and

a fourth bias circuit providing a second fixed voltage when V_PAD is less than a pre-determined value and a voltage higher than the second fixed voltage otherwise.

2. The apparatus of claim 1 further comprising a well biasing circuit which provides a well bias to the upper pair of PMOS devices.

3. The apparatus of claim 2 wherein the well biasing circuit provides a bias voltage of V_DDO if a voltage on the I/O pad is less than V_DDO and provides the voltage on the I/O pad as the bias voltage otherwise.

4. The apparatus of claim 1 further comprising:

a NMOS device having a drain coupled to V_PAD;

the NMOS device having a source coupled to core circuitry; and

having the gate coupled to the fourth bias voltage.