Method and apparatus for acquiring a frequency without a reference clock

• US 6,856,206 B1
• Filed: 06/25/2001
• Issued: 02/15/2005
• Est. Priority Date: 06/25/2001
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Perrott, Michael H.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): GLENN, KIMBERLY E
• Application Number:
  US09/888,663
• Time in Patent Office: 1,331 Days
• Field of Search: 331/1.A, 331/25, 375/376, 375/375, 327/150, 327/2, 327/9, 327/12, 327/8
• US Class Current: 331/25
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04L 1/205 jitter monitoring
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A clock and data recovery system acquires a clock embedded in an input data stream by detecting the occurrence of transitions in the input data stream falling into a predetermined phase zone of a sample clock used to sample the input data stream. A control circuit counts how many evaluation intervals have at least one transition in the predetermined phase zone. The control circuit determines if lock is achieved according to the count. If it is determined that lock is not achieved, an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of evaluation intervals having one or more transitions in the predetermined phase zone is below a level indicating lock.

Claims

1. A method of acquiring timing associated with an input data stream, comprising:

detecting whether transitions of the input data stream fall into a predetermined portion of a sample clock period of a sample clock utilized to sample the input data stream; and

evaluating whether a phase-locked loop (PLL) has acquired the timing of the input data stream according to occurrence of transitions of the input data stream in the predetermined portion of the sample clock period.

2. The method as recited in claim 1 wherein the evaluating further comprises determining over a plurality of time periods, each of the time periods including an increasing number of evaluation intervals, whether the PLL is locked to the timing of the input data stream according to a number of evaluation intervals having one or more transitions in the predetermined portion of the sample clock period.

3. The method as recited in claim 1, wherein the sample clock is a clock recovered from the input data stream.

4. The method as recited in claim 1, wherein the evaluating includes counting a number of evaluation intervals that have at least one transition in the predetermined portion of the clock period, generating a count indicative thereof and determining if lock is achieved according to the count.

5. The method as recited in claim 4 wherein the evaluation intervals are at least as long as a minimum period of frequency offset.

6. The method as recited in claim 4, further comprising comparing the count to a threshold count to determine if lock is achieved.

7. The method as recited in claim 4, further comprising adjusting an output frequency of a variable frequency oscillator circuit if it is determined that lock is not achieved.

8. The method as recited in claim 7, wherein the output frequency is adjusted by changing a variable impedance associated with the oscillator circuit until lock is achieved.

9. The method as recited in claim 8 wherein the variable impedance is changed by adjusting at least a portion of the variable impedance in increasing increments around an initial impedance value.

10. The method as recited in claim 9 further comprising sweeping another portion of the variable impedance linearly for each impedance setting resulting from adjusting at least a portion of the variable impedance in increasing increments around the initial impedance value.

11. The method as recited in claim 8, wherein the variable impedance is a capacitance.

12. The method as recited in claim 11 wherein the oscillator circuit is a tank circuit including an inductive element.

13. The method as recited in claim 7 wherein the oscillator circuit is a ring oscillator.

14. The method as recited in claim 8 wherein the oscillator circuit is a voltage controlled oscillator (VCO).

15. The method as recited in claim 1 wherein the predetermined portion of the clock period is adjacent to a clock edge used to sample the input data stream.

16. An integrated circuit comprising:

means for detecting whether transitions of an input data stream fall into a predetermined portion of a clock period of a clock utilized to sample the input data stream; and

means for evaluating whether a phase-locked loop (PLL) has recovered a timing associated with the input data stream according to occurrence of transitions in the predetermined portion of the clock.

17. The integrated circuit as recited in claim 16 means for evaluating includes means for counting a number of evaluation intervals that have one or more transitions that fall into the predetermined portion of the clock period, generating a count thereof and determining if lock is achieved according to the count.

18. The integrated circuit as recited in claim 16, further comprising means for changing an output frequency of a variable oscillator circuit if it is determined that lock is not achieved.

19. A method of acquiring a clock embedded in an input data stream, comprising varying an output of a variable oscillator until transitions of the input data stream occurring in a predefined phase zone of a sample clock sampling the input data stream occur below an acceptable rate.

20. The method as recited in claim 19 wherein a rate of transitions is determined according to a number of evaluation intervals having one or more transitions occurring in the predefined phase zone.

21. The method as recited in claim 19 wherein the output of the variable oscillator is varied by varying an impedance of the variable oscillator.

22. The method as recited in claim 19 wherein varying the output of the variable oscillator comprises varying at least one of a control voltage and a control current supplied to the variable oscillator.

23. An integrated circuit for receiving an input data stream and locking to a clock embedded in the input data stream using a phase-locked loop, the integrated circuit comprising:

a phase zone detect circuit coupled to determine if a transition of the input data stream occurs in a predetermined phase zone of a sample clock used to sample the input data stream;

a counter circuit coupled to the phase zone detect circuit to supply an indication of a number of evaluation intervals in which at least one bit error occurs;

a compare circuit coupled to compare the indication and a threshold value and to output a compare indication, thereby indicating if the phase-locked loop has locked to the input data stream;

a variable oscillator circuit forming part of the phase-locked loop; and

a control circuit, responsive to the indication that lock is not achieved, to vary the output of the variable oscillator circuit.

24. The integrated circuit as recited in claim 23 wherein:

the phase zone detect circuit includes a first data path and a second data path coupled to receive the input data stream, one of the first and second data paths being delayed with respect to the other, thereby defining the phase zone, and wherein an output signal supplied from the first and second data paths are coupled to a logic circuit to be logically compared.

25. The integrated circuit as recited in claim 23 wherein the first data path is a phase detector circuit coupled to provide an indication of phase error between a recovered clock being used to sample the input data stream and the input data stream.

26. The integrated circuit as recited in claim 24 wherein the one of the first and second data paths is delayed by delaying one of the clock and the data of the input data stream supplied to the one of the first and second data paths.

27. The integrated circuit as recited in claim 23 wherein the second data path includes one or more selector circuits to select from a plurality of clock frequencies.

28. The integrated circuit as recited in claim 24 wherein the first and second data paths are logically compared in an exclusive OR circuit.

29. The integrated circuit as recited in claim 23 further comprising:

a variable impedance circuit forming part of the variable oscillator circuit; and

wherein the control circuit is responsive to the indication that lock is not achieved, to vary the variable impedance circuit to thereby adjust the output of the variable oscillator circuit.

30. The integrated circuit as recited in claim 29 wherein the control circuit adjusts the impedance by changing the impedance to successively above and then below an initial value to provide a gradually increasing swing around an initial impedance value.

31. The integrated circuit as recited in claim 23 wherein the phase-locked loop is determined to be locked to the input data stream if the indication from the count circuit indicates that the number of evaluation intervals in which at least one transition in a predetermined phase zone occurs is below a predetermined threshold value.

32. The integrated circuit as recited in claim 29, wherein the variable impedance is a capacitance.

33. The integrated circuit as recited in claim 23 wherein the oscillator circuit is a tank circuit including an inductive element.

34. The integrated circuit as recited in claim 23 wherein the oscillator circuit is ring oscillator.

35. The integrated circuit as recited in claim 23 wherein the oscillator circuit is a voltage controlled oscillator (VCO).

36. A method comprising determining whether a phase-locked loop (PLL) circuit that is coupled to an input data stream has locked to the input data stream according to whether transitions of the input data stream occur below a predetermined rate in a predetermined portion of a sample clock period of a sample clock utilized to sample the input data stream.

37. An apparatus comprising:

a variable oscillator that is part of a phase-locked loop; and

means coupled to the variable oscillator for determining whether the phase-locked loop has locked to an input data stream according to whether transitions of the input data stream occur in a predetermined portion of a sample clock period at a rate that is below a predetermined rate.

38. A method comprising determining whether a phase-locked loop (PLL) circuit that is coupled to an input data stream has locked to the input data stream according to whether transitions, occurring in a predetermined portion of a sample clock period of a sample clock utilized to sample the input data stream of the input data stream, occur below a predetermined rate.

39. The method as recited in claim 38 further comprising varying an output of a variable oscillator while the phase-locked loop is not locked to the input data stream.