Multi-compare content addressable memory cell

• US 6,856,527 B1
• Filed: 05/30/2003
• Issued: 02/15/2005
• Est. Priority Date: 05/30/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Srinivasan, Varadarajan, Gharia, Nilesh A., Pereira, Jose P.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/448,820
• Time in Patent Office: 627 Days
• Field of Search: 365/49, 365/189.07, 365/210
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A method and apparatus for simultaneously performing a plurality of compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes first and second memory cells to store first and second data, and first and second compare circuits coupled respectively to first and second match lines. The first compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive first comparand data, and a third input coupled to the second memory cell. The second compare circuit has a first input coupled to the first memory cell, a plurality of second inputs to receive second comparand data; and a third input coupled to the second memory cell.

Claims

1. A content addressable memory (CAM) cell comprising:

a first memory cell to store first data;

a second memory cell to store second data;

a first compare circuit coupled to a first match line and having a first input coupled to the first memory cell, a plurality of second inputs to receive first comparand data, and a third input coupled to the second memory cell; and

a second compare circuit coupled to a second match line and having a first input coupled to the first memory cell, a plurality of second inputs to receive second comparand data, and a third input coupled to the second memory cell.

2. The CAM cell of claim 1 wherein the first and second compare circuits are configured to simultaneously compare the first and second comparand data with the first data.

3. The CAM cell of claim 1 wherein the first and second compare circuits are coupled to respective first and second comparand data lines to receive the first and second comparand data.

4. The CAM cell of claim 1 wherein the first comparand data comprises complementary comparand signals, and wherein the first compare circuit comprises a first pair of transistors having control terminals respectively coupled to receive the complementary comparand signals.

5. The CAM cell of claim 4 wherein the first compare circuit comprises a second pair of transistors coupled respectively to the first memory cell and the second memory cell.

6. The CAM cell of claim 5 further comprising a reference node coupled to a reference voltage line, and wherein a first transistor of the first pair of transistors and a first transistor of the second pair of transistors are coupled in series between the first match line and the reference node.

7. The CAM cell of claim 6 wherein a second transistor of the first pair of transistors and a second transistor of the second pair of transistors are coupled in series between the first match line and the reference node.

8. The CAM cell of claim 7 wherein the first transistors of the first and second pairs of transistors are coupled in parallel with the second transistors of the first and second pairs of transistors.

9. The CAM cell of claim 1 wherein the first memory cell is coupled to a first pair of bit lines to receive the first data, and wherein the second memory cell is coupled to a second pair of bit lines to receive the second data.

10. The CAM cell of claim 9 further comprising:

a first pair of transistors coupled between the first pair of bit lines the first memory cell; and

a second pair of transistors coupled between the second pair of bit lines and the second memory cell.

11. The CAM cell of claim 10 wherein control terminals of the first pair of transistors and control terminals of the second pair of transistors are coupled to a first word line.

12. The CAM cell of claim 10 wherein control terminals of the first pair of transistors are coupled to a first word line and control terminals of the second pair of transistors are coupled to a second word line.

13. The CAM cell of claim 1 wherein the first compare circuit comprises:

a first transistor having a first terminal coupled to the first input, a second terminal coupled to a first one of the plurality of second inputs, and a third terminal;

a second transistor having a first terminal coupled to the third input, a second terminal coupled to a second one of the plurality of second inputs, and a third terminal; and

a third transistor having a first terminal coupled to the first match line, a second terminal coupled to a reference voltage line, and a control terminal coupled to the third terminal of the first transistor and to the third terminal of the second transistor.

14. The CAM cell of claim 13 wherein the first terminals of the first and second transistors are control terminals of the first and second transistors.

15. The CAM cell of claim 14 wherein the first and second transistors are metal-oxide-semiconductor (MOS) transistors, and wherein the control terminals of the first and second transistors are gate terminals of the MOS transistors.

16. The CAM cell of claim 15 wherein the second terminals of the first and second transistors are drain terminals of the MOS transistors.

17. The CAM cell of claim 13 wherein the second terminals of the first and second transistors are control terminals of the first and second transistors.

18. The CAM cell of claim 17 wherein the first and second transistors are metal-oxide-semiconductor (MOS) transistors, and wherein the control terminals of the first and second transistors are gate terminals of the MOS transistors.

19. The CAM cell of claim 18 wherein the first terminals of the first and second transistors are drain terminals of the MOS transistors.

20. A content addressable memory (CAM) device comprising:

a plurality of CAM cells arranged in rows and columns, each CAM cell including first and second storage circuits and a plurality of compare circuits, each of the compare circuits having a first input coupled to the first storage circuit and a second input coupled to the second storage circuit; and

a plurality of sets of match lines, each set of match lines corresponding to a respective row of the CAM cells and including a plurality of match lines coupled respectively to the plurality of compare circuits within each CAM cell of the corresponding row of CAM cells.

21. The CAM device of claim 20 further comprising a plurality of sets of compare lines, each set of compare lines corresponding to a respective column of the CAM cells and including a plurality of compare lines coupled respectively to the plurality of compare circuits within each CAM cell of the corresponding column of CAM cells.

22. The CAM device of claim 20 further comprising a plurality of sets of compare lines, each set of compare lines corresponding to a respective column of the CAM cells and including a plurality of pairs of compare lines coupled respectively to the plurality of compare circuits within each CAM cell of the corresponding column of CAM cells.

23. The CAM device of claim 22 wherein each of the plurality of compare circuits within each CAM cell comprises third and fourth inputs coupled respectively to constituent compare lines of one of the plurality of pairs of compare lines.

24. The CAM device of claim 23 wherein each of the compare circuits comprises four transistors having respective control terminals that constitute the first, second, third and fourth inputs of the compare circuit.

25. The CAM device of claim 23 wherein each of the compare circuits comprises:

a first transistor having a first transistor having a first terminal coupled to the first input, a second terminal coupled to the third input, and a third terminal;

a second transistor having a first terminal coupled to the second input, a second terminal coupled to the fourth input, and a third terminal; and

a third transistor having a first terminal coupled to a first match line of the plurality of sets of match lines, a second terminal coupled to a reference voltage line, and a control terminal coupled to the third terminal of the first transistor and to the third terminal of the second transistor.

26. The CAM device of claim 25 wherein the first and second transistors comprise metal-oxide-semiconductor (MOS) transistors and wherein the first terminals of the first and second transistors are gate terminals of the MOS transistors.

27. The CAM device of claim 25 wherein the first and second transistors comprise metal-oxide-semiconductor (MOS) transistors and wherein the second terminals of the first and second transistors are gate terminals of the MOS transistors.

28. A method of operation within a content addressable memory (CAM) device, the method comprising:

signaling a mismatch condition on a first match line if a first data value stored within a first memory cell of the CAM device and a first comparand signal are both at high logic levels;

signaling a mismatch condition on the first match line if a second data value stored within a second memory cell of the CAM device is at a high logic level and the first comparand signal is at a low logic level;

signaling a mismatch condition on a second match line if a second comparand signal and the first data value are both at high logic levels; and

signaling a mismatch condition on the second match line if the second comparand signal is at a low logic level and the second data value is at a logic high level.

29. The method of claim 28 further comprising storing the first and second data values in the first and second memory cells, respectively, within the CAM device.

30. The method of claim 29 wherein storing the first and second data values in the first and second memory cells comprises outputting a first pair of complementary signals representative of the first data value onto a first pair of bit lines coupled to the first memory cell, and outputting a second pair of complementary signals representative of the second data value onto a second pair of bit lines coupled to the second memory cell.

31. The method of claim 30 further comprising:

activating a first word line coupled to the first memory cell to enable the first data value to be stored in the first memory cell in accordance with the state of the first pair of complementary signals; and

activating a second word line coupled to the second memory cell to enable the second data value to be stored in the second memory cell in accordance with the state of the second pair of complementary signals.

32. The method of claim 29 further comprising activating a first word line coupled to the first and second memory cells to simultaneously store the first and second data values in the first and second memory cells, respectively.

33. The method of claim 28 wherein signaling a mismatch condition on a first match line comprises establishing a path between the first match line and a reference voltage node.

34. The method of claim 33 wherein establishing a path between the first match line and the reference voltage node comprises switching at least one transistor coupled between the first match line and a ground voltage node to a conducting state.

35. The method of claim 28 wherein signaling a mismatch condition comprises interrupting a path between the first match line and a reference voltage node.

36. The method of claim 35 wherein interrupting a path between the first match line and the reference voltage node comprises switching at least one transistor coupled between the first match line and the reference voltage node to a substantially non-conducting state.

37. The method of claim 28 wherein signaling the mismatch condition on the first match line and signaling the mismatch condition on the second match line comprises simultaneously signaling the mismatch conditions on the first and second match lines.

38. A content addressable memory (CAM) cell comprising:

a first memory cell to store first data;

a first transistor having a first terminal coupled to the first memory cell, a second terminal coupled to a reference node, and a third terminal coupled to a first intermediate node;

a second transistor having a first terminal coupled to a first compare line, a second terminal coupled to a first match line, and a third terminal coupled to the first intermediate node; and

a third transistor having a first terminal coupled to a second compare line, a second terminal coupled to a second match line, and a third terminal coupled to the first intermediate node.

39. The CAM cell of claim 38 wherein the reference node is coupled to a reference voltage line.

40. The CAM cell of claim 39 wherein the reference voltage line is a ground voltage line.

41. The CAM cell of claim 38 further comprising:

a second memory cell to store mask data; and

a fourth transistor coupled in series with the first and second transistors between the first match line and the reference node, and having a control terminal coupled to the second memory cell.

42. The CAM cell of claim 38 further comprising:

a second memory cell to store mask data; and

a fourth transistor coupled between the first compare line and the first terminal of the second transistor, the fourth transistor having a control terminal coupled to the second memory cell.

43. The CAM cell of claim 38 further comprising:

a second memory cell to store mask data; and

a fourth transistor coupled between the first memory cell and the first terminal of the first transistor, the fourth transistor having a control terminal coupled to the second memory cell.

44. The CAM cell of claim 38 further comprising:

a fourth transistor having a first terminal, a second terminal coupled to the reference node, and a third terminal coupled to a second intermediate node;

a fifth transistor having a first terminal coupled to a third compare line, a second terminal coupled to the first match line, and a third terminal coupled to the second intermediate node; and

a sixth transistor having a first terminal coupled to a fourth compare line, a second terminal coupled to the second match line and a third terminal coupled to the second intermediate node.

45. The CAM cell of claim 44 further comprising a second memory cell to store second data and wherein the first terminal of the fourth transistor is coupled to the second memory cell.

46. The CAM cell of claim 44 wherein the first terminal of the fourth transistor is coupled to the first memory cell.

47. The CAM cell of claim 46 wherein the first memory cell comprises a first output coupled to the first terminal of the first transistor, and a second output coupled to the first terminal of the fourth transistor, the first memory cell being configured to output the first data and a complement of the first data via the first and second outputs, respectively.

48. The CAM cell of claim 44 wherein the reference node is coupled to a reference voltage line.

49. The CAM cell of claim 38 wherein each of the first, second and third transistors is a metal oxide semiconductor (MOS) transistor.

50. A content addressable memory (CAM) cell comprising:

a first memory cell;

a second memory cell;

a first compare circuit coupled to a first match line and having a first transistor coupled to the first memory cell, and a second transistor coupled to the second memory cell; and

a second compare circuit coupled to a second match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell.

51. The compare circuit of claim 50 wherein the first compare circuit has third and fourth transistors coupled respectively to first and second compare lines, and wherein the second compare circuit has third and fourth transistors coupled to third and fourth compare lines.

52. The compare circuit of claim 51 wherein the first and third transistors of the first compare circuit are coupled in series between the first match line and a first reference node, and wherein the second and fourth transistors of the first compare circuit are coupled in series between the first match line and the first reference node.

53. The compare circuit of claim 52 wherein the first reference node is coupled to a ground reference.

54. The compare circuit of claim 52 wherein the first and third transistors of the second compare circuit are coupled in series between the second match line and a second reference node, and wherein the second and fourth transistors of the second compare circuit are coupled in series between the second match line and the second reference node.

55. The compare circuit of claim 54 wherein the first and second reference nodes are coupled to one another.

56. A content addressable memory (CAM) cell comprising:

means for storing a first data value;

means for storing a second data value;

means for signaling a mismatch condition on a first match line if the first data value and a first comparand signal are both at high logic levels;

means for signaling a mismatch condition on the first match line if the second data value is at a high logic level and the first comparand signal is at a low logic level;

means for signaling a mismatch condition on a second match line if the first data value and a second comparand signal are both at high logic levels; and

means for signaling a mismatch condition on the second match line if the second data value is at a high logic level and the second comparand signal is at a low logic level.

57. The CAM cell of claim 56 wherein the means for signaling a mismatch condition on the first match line comprises means for establishing a path between the first match line and a reference voltage node.

58. The CAM cell of claim 56 wherein the means for establishing a path between the first match line and the reference voltage node comprises means for establishing a path between the first match line and a ground node.

59. The CAM cell of claim 56 wherein the means for signaling a mismatch condition on the first match line comprises means for interrupting a path between the first match line and a reference voltage node.

60. The CAM cell of claim 56 wherein the means for signaling the mismatch condition on the first match line and the means for signaling the mismatch condition on the second match line are configured to simultaneously signal the mismatch conditions on the first and second match lines.