Multi-state memory
First Claim
1. A multi-state memory, comprising:
- a plurality of EEPROM memory cells, each of said memory cells coupled to a word line and to a bit line and able to store one of a plurality of multi-states, organized into a plurality of sectors;
at least one tracking cell for each of said multi-states, associated with each of said plurality of sectors;
read circuitry to read raw data associated with a programmed state of said tracking cell;
converter circuitry to convert said raw data to digital form;
circuitry to precharge said bit line coupled to a selected plurality of said memory cells and to then turn-on said word line coupled to selected said memory cells using a word line signal;
wherein discharge rate of potential on said bit line provides a measure of program drive for said memory cell; and
a memory controller to establish desired read points for each of a plurality of physical states, based upon digitally converted read said raw data from each said tracking cell.
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Accused Products
Abstract
Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
308 Citations
73 Claims
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1. A multi-state memory, comprising:
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a plurality of EEPROM memory cells, each of said memory cells coupled to a word line and to a bit line and able to store one of a plurality of multi-states, organized into a plurality of sectors;
at least one tracking cell for each of said multi-states, associated with each of said plurality of sectors;
read circuitry to read raw data associated with a programmed state of said tracking cell;
converter circuitry to convert said raw data to digital form;
circuitry to precharge said bit line coupled to a selected plurality of said memory cells and to then turn-on said word line coupled to selected said memory cells using a word line signal;
wherein discharge rate of potential on said bit line provides a measure of program drive for said memory cell; and
a memory controller to establish desired read points for each of a plurality of physical states, based upon digitally converted read said raw data from each said tracking cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 57, 61, 62, 63, 64)
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30. A method to implement multi-state memory, comprising the following steps:
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providing a plurality of EEPROM memory cells, each of said memory cells coupled to a word line and to a bit line and able to store one of a plurality of multi-states, organized into a plurality of sectors;
providing at least one tracking cell for each of said multi-states, associated with each of said plurality of sectors;
reading read raw data associated with a programmed state of said tracking cell;
converting said raw data to digital form;
precharging said bit lines coupled to a selected plurality of said memory cells and turning-on said word line coupled to selected said memory cells using a word line signal;
wherein discharge rate of potential on said bit line provides a measure of program drive for said memory cell; and
using a memory controller to establish desired read points for each of a plurality of physical states, based upon digitally converted read said raw data from each said tracking cell. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 58, 59, 60)
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65. A method of reading programmed states of a selected plurality of an array of non-volatile erasable and re-programmable memory cells that are operably connected with respective bit lines and which have word lines extending thereacross, comprising:
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pre-charging at least some of the bit lines that are operably connected with the selected memory cells to a pre-charged level, thereafter changing voltages of those of the word lines that are operably connected with the selected memory cells from non-selected levels to selected levels, while maintaining others of the word lines at non-selected levels, thereafter allowing the pre-charged bit lines to discharge through the selected memory cells to a predetermined level, and individually measuring durations of the discharge of the pre-charged bit lines to the predetermined level, thereby to provide individual measures of the programmed states of the selected memory cells. - View Dependent Claims (66, 67, 68, 69, 70, 71)
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72. A method of reading programmed states of a selected plurality of an array of erasable and re-programmable non-volatile memory cell, comprising:
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applying a voltage condition to an element of the individual selected memory cells, removing the voltage condition from the selected memory cells, after removal of the voltage condition, monitoring a parameter that changes for the selected memory cells in accordance with their individual programmed states, and measuring relative durations of the changing parameter of the selected memory cells, thereby to provide indications of their programmed states. - View Dependent Claims (73)
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Specification