Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data

• US 6,856,550 B2
• Filed: 11/19/2002
• Issued: 02/15/2005
• Est. Priority Date: 05/23/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kato, Hiroshi, Taito, Yasuhiko, Ooishi, Tsukasa, Ohtani, Jun
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/298,666
• Publication Number:
  US 20030218897A1
• Time in Patent Office: 819 Days
• Field of Search: 365/185.01, 365/185.28, 365/185.22, 365/185.24, 365/185.03, 365/205, 365/189.01
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

At the time of an operation of writing data to a specific memory cell in a memory block, a semiconductor memory device applies a write voltage for a predetermined period and, after that, performs a verifying operation by using a sense amplifier circuit and a comparator. When it is found as a result of the verifying operation that writing to the memory cell is insufficient, the writing operation is performed again by an instruction of a memory control circuit. At this time, the memory control circuit adjusts a write voltage.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix;

a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells;

a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells; and

a control circuit for performing a writing operation on said plurality of memory cells at the time of a writing operation, wherein

each of said plurality of memory cells includes;

first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines; and

an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and

said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells,

the memory device further comprising a counter for counting the number of times said control circuit has performed the writing operation since the memory device was shipped, wherein

said control circuit varies the magnitude of a pulse voltage to be applied to a selected memory cell based on the number of times counted by said counter.

2. The nonvolatile semiconductor memory device according to claim 1, further comprising

a verifying circuit for performing a verifying operation on said selected memory cell each time said control circuit applies said pulse voltage.

3. The nonvolatile semiconductor memory device according to claim 2, wherein

a voltage applied to said first conductive region at the time of the writing operation is higher than a voltage applied to said second conductive region, and a voltage applied to said first conductive region at the time of a reading operation is lower than a voltage applied to said second conductive region.

4. The nonvolatile semiconductor memory device according to claim 3, further comprising

a count circuit for counting the number of said pulse voltages applied by said control circuit to said selected memory cell, wherein

said count circuit stops operation of said control circuit when the number of pulse voltages applied to said selected memory cell exceeds a predetermined number of times in each writing operation.

5. The nonvolatile semiconductor memory device according to claim 1, further comprising

a sense amplifier circuit for reading data stored in each of said plurality of memory cells.

6. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix;

a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells;

a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells; and

a control circuit for performing a writing operation on said plurality of memory cells at the time of a writing operation, wherein

each of said plurality of memory cells includes;

first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines; and

an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and

said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells,

said nonvolatile semiconductor memory device further comprising a sense amplifier circuit for reading data stored in each of said plurality of memory cells, wherein

said sense amplifier circuit is a single end type sense amplifier circuit.

7. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix;

a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells;

a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells; and

a control circuit for performing a writing operation on said plurality of memory cells at the time of a writing operation, wherein

each of said plurality of memory cells includes;

first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines; and

an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and

said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells,

said nonvolatile semiconductor memory device further comprising a sense amplifier circuit for reading data stored in each of said plurality of memory cells, wherein

said sense amplifier circuit includes a differential amplifier circuit which receives data of each of said plurality of memory cells and a reference potential.

8. The nonvolatile semiconductor memory device according to claim 7, wherein

said sense amplifier circuit further includes a reference potential generating circuit for generating said reference potential, and

said reference potential generating circuit includes a plurality of reference cells operating at the time of a reading or writing operation.

9. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of memory blocks including a plurality of nonvolatile memory cells arranged in a matrix;

a plurality of word lines arranged in correspondence with a row direction of said plurality of memory cells;

a plurality of bit lines arranged in correspondence with a column direction of said plurality of memory cells; and

a control circuit for performing a writing operation on said plurality of memory cells at the time of a writing operation, wherein

each of said plurality of memory cells includes;

first and second conductive regions formed in a main surface of said semiconductor substrate and connected to corresponding bit lines in said plurality of bit lines; and

an insulating film formed on said semiconductor substrate between said first and second conductive regions, having a first storing region in the vicinity of said first conductive region and a second storing region in the vicinity of said second conductive region, and

said control circuit applies at least one pulse voltage to a selected memory cell in said plurality of memory cells,

said nonvolatile semiconductor memory device further comprising a sense amplifier circuit for reading data stored in each of said plurality of memory cells, wherein

said sense amplifier circuit includes;

a differential amplifier circuit which receives data of each of said plurality of memory cells and a reference potential; and

a reference potential generating circuit for generating said reference potential, said reference potential generating circuit including a plurality of reference cells operating at the time of a reading or writing operation, wherein

said plurality of reference cells includes;

a read reference cell operating in a reading operation; and

a write reference cell operating in a writing operation and having a threshold value different from that of said read reference cell.

10. The nonvolatile semiconductor memory device according to claim 9, wherein

the threshold value of said write reference cell is higher than the threshold value of said read reference.