Low resistivity copper conductor line, liquid crystal display device having the same and method for forming the same

• US 6,858,479 B2
• Filed: 12/20/2002
• Issued: 02/22/2005
• Est. Priority Date: 03/07/2002
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Soo-Kil, Kim, Jae-Jeong, Kim, Yong-Shik
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/323,946
• Publication Number:
  US 20030171003A1
• Time in Patent Office: 795 Days
• Field of Search: 438/158, 438/642, 438/643, 438/650, 438/652, 438/653, 438/656, 438/674, 438/685, 438/686, 438/687
• US Class Current: 438/158
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1078 Multiple stacked thin films not being formed in openings in dielectrics
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A method for forming a low resistively copper conductor line includes forming a silver material layer on silicon material, and forming a copper material layer on the silver material layer using an electroplating process.

Claims

1. A method for forming a low resistively copper conductor line, comprising:

forming a silver material layer directly on silicon material;

etching the silver material layer; and

forming a copper material layer on the etched silver material layer using an electroplating process.

2. A method for forming a low resistively copper conductive line for a liquid crystal display (LCD) device, comprising:

forming a silicon layer on a substrate;

forming a silver layer on the silicon layer using a deposition process;

patterning the silver layer into a first shape; and

forming a copper layer on the silver layer by an electroplating process using the silver layer as a seed layer.

3. The method according to claim 2, wherein a thickness of the silver layer is about 50 nm.

4. The method according to claim 2, wherein a specific resistance of the copper conductive line is between about 2.93 μ

Ω

·

cm and about 3.27 μ

Ω

·

cm.

5. A method for forming a low resistively copper conductive line for a semiconductor element, comprising:

forming a silver thin film directly on a silicon layer by depositing silver directly on the silicon layer;

patterning the silver thin film into a first shape; and

forming a copper thin film on the silver thin film by an electroplating process using the silver thin film as a seed layer.

6. The method according to claim 5, wherein a thickness of the silver thin film is about 50 nm.

7. The method according to claim 5, wherein a specific resistance of the copper conductive line is between about 2.93 μ

Ω

·

cm and about 3.27 μ

Ω

·

cm.

8. A method for fabricating an array substrate of a liquid crystal display device, comprising:

forming a first silver thin film by depositing and patterning silver on a substrate;

forming a copper thin film on the first silver thin film by an electroplating process using the first silver thin film as a seed layer to form a gate line and gate electrode;

forming a gate insulating layer on an entire surface of the substrate;

forming an active layer and an ohmic contact layer sequentially on the gate insulating layer;

forming a second silver thin film by depositing and patterning silver on the substrate;

forming a copper thin film on the second silver thin film by an electroplating process using the second silver thin film as a seed layer to form a data line, and source and drain electrodes;

forming a passivation layer on an entire surface of the substrate;

patterning the passivation layer to expose a portion of the drain electrode; and

forming a pixel electrode on the passivation layer to electrically contact the drain electrode.

9. The method according to claim 8, wherein a thickness of both the first and second silver thin films is about 50 nm.

10. The method according to claim 8, wherein specific resistances of both the gate line and the data line are between about 2.93 μ

Ω

·

cm and about 3.27 μ

Ω

·

cm.

11. The method according to claim 8, further comprising a step of forming a metal pattern over the gate line that electrically contacts the pixel electrode.