Method of forming a dual-sided capacitor

• US 6,858,493 B2
• Filed: 05/30/2003
• Issued: 02/22/2005
• Est. Priority Date: 08/22/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ping, Er-Xuan, Chen, Shenlin
• Primary Examiner(s): PHAM, HOAI V
• Application Number:
  US10/448,115
• Publication Number:
  US 20040036099A1
• Time in Patent Office: 634 Days
• Field of Search: 438/239, 438/240, 438/253, 438/254, 438/255, 438/396, 438/397, 438/398, 257/303, 257/304, 257/306, 257/309, 257/310
• US Class Current: 438/253
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Claims

1. A method of forming a capacitor comprising:

forming a doped polycrystalline layer over a substrate;

forming a native oxide layer over said doped polycrystalline layer;

forming a layer of hemispherical grained polysilicon over said native oxide layer;

forming a dielectric layer over at least a portion of an outer side of said doped polycrystalline layer and said layer of hemispherical grained polysilicon; and

forming a conductive layer over said dielectric layer.

2. The method of claim 1, wherein said step of forming said dielectric layer further comprises the step of exposing said at least a portion of said outer side of said doped polycrystalline layer.

3. The method of claim 1, wherein said doped polycrystalline layer is formed of a material selected from the group consisting of hemispherical grained polysilicon, silicon, germanium, or any alloy of silicon and germanium.

4. The method of claim 1, wherein said native oxide layer is formed to a thickness of about 5 Angstroms to about 50 Angstroms.

5. The method of claim 1, wherein said native oxide layer is formed between said doped polycrystalline layer and said layer of hemispherical grained polysilicon.

6. The method of claim 1, wherein said native oxide layer is formed by an in-situ oxidation of said doped polycrystalline layer.

7. The method of claim 1, wherein said native oxide layer is formed by an in-situ oxidation of said doped polycrystalline layer under a low partial pressure.

8. The method of claim 7, wherein said native oxide layer is formed by an in-situ oxidation of said doped polycrystalline layer for about 1-5 minutes.

9. The method of claim 1, wherein said native oxide layer is thermally grown.

10. The method of claim 1, wherein said native oxide layer is formed by atomic layer deposition.

11. The method of claim 1, wherein said act of forming said layer of hemispherical grained polysilicon further comprises depositing an amorphous layer of polysilicon over said native oxide layer.

12. The method of claim 11 further comprising annealing said amorphous layer of polysilicon to form said layer of hemispherical grained polysilicon.

13. The method of claim 12, wherein said anneal is a PH₃ anneal.

14. A method of forming a dual-sided capacitor comprising:

forming an opening in an insulating layer;

forming a doped polysilicon layer within said opening;

forming a native oxide layer over said doped polysilicon layer;

forming a layer of hemispherical grained polysilicon over said native oxide layer;

removing at least a portion of said insulating layer to expose at least a portion of an outer side of said doped polysilicon layer;

forming a layer comprising a high-dielectric constant material over said exposed portion of said doped polysilicon layer and over said layer of hemispherical grained polysilicon; and

forming a conductive layer over said layer comprising a high-dielectric constant material.

15. The method of claim 14, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer.

16. The method of claim 14, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer under a low partial pressure.

17. The method of claim 16, wherein said low partial pressure is of about 10⁻

6 Torr.

18. The method of claim 16, wherein said native oxide layer is formed by an in-situ oxidation of said doped polysilicon layer under a low partial pressure of about 10⁻

6 Torr and for about 1-5 minutes.

19. The method of claim 14, wherein said native oxide layer is thermally grown.

21. The method of claim 14, wherein said act of forming said layer of hemispherical grained polysilicon further comprises depositing an amorphous layer of polysilicon over said native oxide layer.

22. The method of claim 21 further comprising annealing said amorphous layer of polysilicon to form said layer of hemispherical grained polysilicon.

23. The method of claim 22, wherein said anneal is a PH₃ anneal.

20. The method of claim wherein said native oxide layer is formed by atomic layer deposition.