Efficient ESD protection with application for low capacitance I/O pads

• US 6,858,902 B1
• Filed: 10/31/2003
• Issued: 02/22/2005
• Est. Priority Date: 10/31/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Duvvury, Charvaka, Salling, Craig T.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US10/698,633
• Time in Patent Office: 480 Days
• Field of Search: 257/360, 257/361, 257/362, 257/359, 361/53, 361/54, 361/55, 361/56
• US Class Current: 257/360
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/027 specially adapted to provide an electrical current path other than the field effect induced current path

Abstract

A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.

Claims

1. A semiconductor device for protecting an integrated circuit input/output pad against ESD events, comprising:

a substrate of a first conductivity type, said substrate having a resistivity;

a multi-finger MOS transistor in said substrate, said MOS transistor comprising a source region, connected to ground potential, a gate region, connected to ground potential, and a drain region, connected to said pad;

a well of the opposite conductivity type in said substrate, said well positioned in close proximity to said transistor regions;

an interdigitated diode in said well, said diode having a plurality of anode regions of said first conductivity type, connected to said pad and said drain, and a plurality of cathode regions of said opposite conductivity type, connected to power;

each transistor region aligned with a corresponding diode region such that said diode-anode regions are positioned at a close proximity to said source regions, and said diode-cathode regions positioned at said close proximity to said drain regions;

each of said transistor and diode regions, respectively, coupled by said proximity and said connections, creating a localized parasitic silicon-controlled rectifier (SCR) comprising an SCR-anode formed by said diode-anode, a first base region formed by said well, a second base region formed by said substrate, and an SCR-cathode formed by said transistor source, said SCR operable to distribute an ESD current at low voltage.

2. The device according to claim 1 wherein said first conductivity type is p-type and said opposite conductivity type is n-type.

3. The device according to claim 2 wherein said substrate is a p-type substrate, said MOS transistor an nMOS transistor, said diode a pn-diode, and said silicon controlled rectifier a pnpn-SCR.

4. The device according to claim 1 wherein said proximity comprises a distance selected for SCR effectiveness in conjunction with said substrate resistivity.

5. The device according to claim 4 wherein said proximity comprises a distance of less than 5 μ

m for substrate sheet resistances in the range from about 200 to 500 Ω

/□

.

6. The device according to claim 1 wherein said MOS transistor is interconnected as a cascode for voltage tolerant protection, said cascoded MOS transistor having a cascode-source, connected to ground potential, and a cascode-drain, connected to said pad.

7. The device according to claim 1 wherein said at least one diode determines said proximity for efficient SCR functionality.

8. The device according to claim 1 further comprising a guard ring at a certain distance from said transistor and said diode, said guard ring connected to ground potential and operable to provide the local substrate resistance, based on said substrate resistivity, of said SCR to ground potential.

9. The device according to claim 8 wherein said guard ring provides an effective substrate resistance between about 50 and 500 Ω

.

10. A semiconductor device for ESD protection of an input/output pad, comprising:

a substrate of a first conductivity type said substrate having a resistivity;

a multi-finger MOS transistor in said substrate, said MOS transistor comprising a source region, connected to ground potential, a gate region, connected to ground potential, and a drain region, connected to power;

a first well of the opposite conductivity type in said substrate, said well positioned in close proximity to said transistor regions;

a first interdigitated diode in said first well, said first diode having a plurality of first anode regions of said first conductivity type, connected to said pad, and a plurality of first cathode regions of said opposite conductivity type, connected to power;

each transistor region aligned with a corresponding first diode region such that said first diode-anode regions are positioned at a close proximity to said source regions, and said first diode-cathode regions positioned at said close proximity to said drain regions;

each of said transistor and first diode regions, respectively, coupled by said proximity and said connections, creating a localized parasitic silicon-controlled rectifier (SCR) comprising an SCR-anode formed by said first diode anode, a first base region formed by said first well, a second base region formed by said substrate, and an SCR-cathode formed by said transistor source;

a second well of the opposite conductivity type in said substrate; and

a second diode in said second well, said second diode having a second anode, connected to ground potential, and a second cathode, connected to said pad.

11. The device according to claim 10 further comprising an additional clamp between said power and said ground potential to protect against direct ESD stress.

12. The device according to claim 10 wherein said first conductivity type is p-type and said opposite conductivity type is n-type.

13. The device according to claim 12 wherein said substrate is a p-type substrate, said MOS transistor an NMOS transistor, said first and second diodes pn-diodes, and said silicon controlled rectifier a pnpn-SCR.

14. The device according to claim 10 wherein said proximity comprises a distance selected for SCR effectiveness in conjunction with said substrate resistivity.

15. The device according to claim 14 wherein said proximity comprises a distance of less than 5 μ

m for substrate resistivities in the range from about 200 to 500 Ω

cm.

16. The device according to claim 10 wherein said MOS transistor is interconnected as a cascode for voltage tolerant protection, said cascoded MOS transistor having a cascode-source, connected to ground potential, and a cascode-drain, connected to said pad.

17. The device according to claim 10 wherein said first diode determines said proximity for efficient SCR functionality.

18. The device according to claim 10 further comprising a guard ring at a certain distance from said transistor and said diode, said guard ring connected to ground potential and operable to provide the local substrate resistance, based on said substrate resistivity, of said SCR to ground potential.

19. The device according to claim 18 wherein said guard ring provides an effective substrate resistance between about 50 to 500 Ω

.