Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers

• US 6,858,906 B2
• Filed: 06/27/2002
• Issued: 02/22/2005
• Est. Priority Date: 06/28/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jung-Dal, Lee, Chang-Hyun, Ye, Byoung-Woo
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US10/184,328
• Publication Number:
  US 20030047755A1
• Time in Patent Office: 971 Days
• Field of Search: 257/406, 257/405, 257/407, 257/408, 257/315, 257/316, 257/317, 257/200
• US Class Current: 257/406
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.

Claims

1. A floating trap non-volatile memory device comprising:

a semiconductor substrate;

a tunneling insulating layer having a first dielectric constant on the substrate;

a charge storage layer on the tunneling insulating layer;

a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunneling insulting layer; and

a gate electrode on the blocking insulating layer.

2. The memory device of claim 1, further comprising a pair of impurity-doped layers in the substrate adjacent to opposite sides of the gate electrode.

3. The memory device of claim 1, wherein the tunneling insulating layer includes silicon oxide.

4. The memory device of claim 1, wherein the blocking insulating layer includes at least one of a metallic oxide material and a metallic oxynitride material of a group III element or group VB element.

5. The memory device of claim 1, wherein the blocking insulating layer is a metal oxide material doped with a group IV element.

6. The memory device of claim 5, wherein the group IV element is one of Zr, Si, Ti, and Hf.

7. The memory device of claim 1, wherein the blocking insulating layer is one of HfO₂, Hf_1-xAl_xO_y, Al₂O₃, La₂O₃, Hf_xSi_1-xO₂, Hf—

Si-oxynitride, ZrO₂, Zr_xSi_1-xO₂, Zr—

Si-oxynitride, and combinations thereof.

8. The memory device of claim 1, wherein the blocking insulating layer is one of Ta₂O₅, TiO₂, PZT[Pb (Zi,Ti)O₃], PbTiO₃, PbZrO₃, La-doped PZT[(Pb,La)(Zi,Ti)O₃], PbO, SrTiO₃, BaTiO₃, BST[(Ba,Sr)TiO₃], SBT (SrBi₂Ta₂O₉), and Bi₄Ti₃O₁₂, and combinations thereof.

9. The memory device of claim 1, wherein the blocking insulating layer comprises a first blocking layer of a first material and a second blocking layer of a second material, the second material having a different dielectric constant than the first material.

10. The memory device of claim 1, wherein the blocking insulating layer includes:

a dielectric layer; and

a silicon oxide layer between the charge storage layer and the dielectric layer.

11. The memory device of claim 1, wherein the blocking insulating layer includes:

a dielectric layer; and

a silicon oxide layer between the dielectric layer and the gate electrode.

12. The memory device of claim 1, wherein the blocking insulating layer includes:

a dielectric layer;

a second silicon oxide layer between the charge storage layer and the dielectric layer; and

a first silicon oxide layer between the dielectric layer and the gate electrode.

13. The memory device of claim 1, wherein the charge storage layer is one of Si₃N₄, silicon oxynitride, silicon-rich SiO₂, and a ferroelectric material.

29. The memory device of claim 1, wherein the blocking insulating layer consists of a dielectric material having a second dielectric constant.

14. A floating trap non-volatile memory device comprising:

a semiconductor substrate;

a plurality of parallel active regions on the semiconductor substrate;

a plurality of parallel memory gate electrodes that intersect and pass over the active regions;

a tunneling insulating layer having a first dielectric constant;

a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant of the tunneling insulating layer; and

a charge storage layer, wherein the tunneling insulating layer, the charge storage layer, and the blocking insulating layer are between the intersections of the active regions and the memory gate electrodes.

15. The memory device of claim 14, further comprising a pair of impurity-doped layers in the substrate adjacent to opposite sides of each of the memory gate electrodes.

16. The memory device of claim 14, further comprising:

a string selection gate electrode;

a ground selection gate electrode, wherein the memory gate electrodes are between the string selection gate electrode and the ground selection gate electrode.

17. The memory device of claim 14, further comprising a gate insulating layer between the string selection gate electrode and the active regions, and between the ground selection gate electrode and the active regions.

18. The memory device of claim 14, further comprising a tunneling insulating layer, a charge storage layer, and a blocking insulating layer sequentially stacked between the string selection gate electrode and the respective active regions and between the ground selection gate electrode and the respective active regions.

19. The memory device of claim 14, wherein the tunneling insulating layer includes a silicon thermal oxide material.

20. The memory device of claim 14, wherein the blocking insulating layer includes at least one of a metallic oxide material and a metallic oxynitride material of a group III element or group VB element.

21. The memory device of claim 14, wherein the blocking insulating layer is a metal oxide material doped with a group IV element.

22. The memory device of claim 21, wherein the group IV element is one of Zr, Si, Ti, and Hf.

23. The memory device of claim 14, wherein the blocking insulating layer is one of HfO₂, Hf_1-xAl_xO_y, Al₂O₃, La₂O₃, Hf_xSi_1-xO₂, Hf—

Si-oxynitride, ZrO₂, Zr_xSi_1-xO₂, Zr—

Si-oxynitride, and combinations thereof.

24. The memory device of claim 14, wherein the blocking insulating layer is one of Ta₂O₅, TiO₂, PZT[Pb (Zi,Ti)O₃], PbTiO₃, PbZrO₃, La-doped PZT[(Pb,La)(Zi,Ti)O₃], PbO, SrTiO₃, BaTiO₃, BST[(Ba,Sr)TiO₃], SBT (SrBi2Ta₂O₉), and Bi₄Ti₃O₁₂, and combinations thereof.

25. The memory device of claim 14, wherein the blocking insulating layer includes:

a dielectric layer; and

a silicon oxide layer between the charge storage layer and the dielectric layer.

26. The memory device of claim 14, wherein the blocking insulating layer includes:

a dielectric layer; and

a silicon oxide layer between the dielectric layer and the memory gate electrodes.

27. The memory device of claim 14, wherein the blocking insulating layer includes:

a dielectric layer;

a second silicon oxide layer between the charge storage layer and the dielectric layer; and

a first silicon oxide layer between the dielectric layer and the memory gate electrodes.

28. The memory device of claim 14, wherein the charge storage layer is one of Si3N4, silicon oxynitride, silicon-rich SiO2, and ferroelectric material.

30. A floating trap non-volatile memory device comprising:

a semiconductor substrate;

a tunneling insulating layer having a first dielectric constant on the substrate;

a charge storage layer on the tunneling insulating layer, the charge storage layer having a plurality of trap energy levels;

a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunneling insulting layer; and

a gate electrode on the blocking insulating layer.